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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Blame information for rev 486

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#include "spr-defs.h"
#include "board.h"
 
/* ======================================================= [ macros ] === */
 
#define REDZONE 128
#define EXCEPTION_STACK_SIZE (128 + REDZONE)
 
#define CLEAR_GPR(gpr) \
        l.or    gpr, r0, r0
 
#define ENTRY(symbol)    \
        .global symbol ; \
symbol:
 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)  \
        .global symbol ;               \
        l.movhi gpr, hi(symbol) ;      \
        l.ori   gpr, gpr, lo(symbol)
 
        // Really goes to configurable interrupt handler
#define EXCEPTION_HANDLER            \
        l.addi  r1, r1, -EXCEPTION_STACK_SIZE;          \
        l.sw    4(r1), r3;             \
        l.sw    8(r1), r4;             \
        l.mfspr r3,r0,SPR_NPC;          \
        l.mfspr r4,r0,SPR_EPCR_BASE;   \
        l.j default_exception_handler; \
        l.nop
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        l.movhi r1, 0
        l.movhi r2, 0
        l.movhi r3, 0
        l.movhi r4, 0
        l.movhi r5, 0
        l.movhi r6, 0
        l.movhi r7, 0
        l.movhi r8, 0
        l.movhi r9, 0
        l.movhi r10, 0
        l.movhi r11, 0
        l.movhi r12, 0
        l.movhi r13, 0
        l.movhi r14, 0
        l.movhi r15, 0
        l.movhi r16, 0
        l.movhi r17, 0
        l.movhi r18, 0
        l.movhi r19, 0
        l.movhi r20, 0
        l.movhi r21, 0
        l.movhi r22, 0
        l.movhi r23, 0
        l.movhi r24, 0
        l.movhi r25, 0
        l.movhi r26, 0
        l.movhi r27, 0
        l.movhi r28, 0
        l.movhi r29, 0
        l.movhi r30, 0
        l.movhi r31, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Early Stack initilization */
        LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
 
        /* Jump to program initialisation code */
        LOAD_SYMBOL_2_GPR(r4, _start)
        l.jr    r4
        l.nop
 
/* ---[ 0x200: BUS exception ]------------------------------------------- */
        .org 0x200
        EXCEPTION_HANDLER
 
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
        .org 0x300
        EXCEPTION_HANDLER
 
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
        .org 0x400
        EXCEPTION_HANDLER
 
 
/* ---[ 0x500: Timer exception ]----------------------------------------- */
        .org 0x500
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        //EXCEPTION_HANDLER
        /* Simply load timer_ticks variable and increment */
        .extern timer_ticks
        l.addi  r1, r1, -136
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(timer_ticks)
        l.ori   r25, r25, lo(timer_ticks)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 136
        l.rfe
 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
        .org 0x600
        EXCEPTION_HANDLER
 
/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
        .org 0x700
        EXCEPTION_HANDLER
 
/* ---[ 0x800: External interrupt exception ]---------------------------- */
        .org 0x800
        EXCEPTION_HANDLER
 
/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
        .org 0x900
        EXCEPTION_HANDLER
 
/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
        .org 0xa00
        EXCEPTION_HANDLER
 
/* ---[ 0xb00: Range exception ]----------------------------------------- */
        .org 0xb00
        EXCEPTION_HANDLER
 
/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
        .org 0xc00
        EXCEPTION_HANDLER
 
/* ---[ 0xd00: FPU exception ]------------------------------------------- */
        .org 0xd00
        EXCEPTION_HANDLER
 
/* ---[ 0xe00: Trap exception ]------------------------------------------ */
        .org 0xe00
        EXCEPTION_HANDLER
 
/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */
/*
        .org 0xf00
        EXCEPTION_HANDLER
 
        .org 0x1000
        EXCEPTION_HANDLER
 
        .org 0x1100
        EXCEPTION_HANDLER
 
        .org 0x1200
        EXCEPTION_HANDLER
 
        .org 0x1300
        EXCEPTION_HANDLER
 
        .org 0x1400
        EXCEPTION_HANDLER
 
*/
/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */
/*
        .org 0x1500
        EXCEPTION_HANDLER
 
        .org 0x1600
        EXCEPTION_HANDLER
 
        .org 0x1700
        EXCEPTION_HANDLER
 
        .org 0x1800
        EXCEPTION_HANDLER
*/
/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */
/*
        .org 0x1900
        EXCEPTION_HANDLER
 
        .org 0x1a00
        EXCEPTION_HANDLER
 
        .org 0x1b00
        EXCEPTION_HANDLER
 
        .org 0x1c00
        EXCEPTION_HANDLER
 
        .org 0x1d00
        EXCEPTION_HANDLER
 
        .org 0x1e00
        EXCEPTION_HANDLER
 
        .org 0x1f00
        EXCEPTION_HANDLER
*/
 
/* ========================================================= [ entry ] === */
        .section .text
 
ENTRY(_start)
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
 
        /* Clear BSS */
        LOAD_SYMBOL_2_GPR(r28, _bss_start)
        LOAD_SYMBOL_2_GPR(r30, _bss_end)
1:
        l.sw    (0)(r28), r0
        l.sfltu r28, r30
        l.bf    1b
        l.addi  r28, r28, 4
 
        /* Initialise UART in a C function */
        /*l.jal    _uart_init
        l.nop*/
 
        /* Jump to main program entry point (argc = argv = 0) */
        CLEAR_GPR(r3)
        CLEAR_GPR(r4)
        l.jal   main
        l.nop
 
        /* If program exits, call exit routine */
        l.addi  r3, r11, 0
        l.jal   exit
        l.nop
 
 
/* ====================================== [ default exception handler ] === */
 
default_exception_handler:
        l.sw    0x00(r1), r2
        l.sw    0x0c(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
        l.sw    0x78(r1), r32
 
        l.jal   default_exception_handler_c
        l.nop
 
        l.lwz    r2, 0x00(r1)
        l.lwz    r3, 0x04(r1)
        l.lwz    r4, 0x08(r1)
        l.lwz    r5, 0x0c(r1)
        l.lwz    r6, 0x10(r1)
        l.lwz    r7, 0x14(r1)
        l.lwz    r8, 0x18(r1)
        l.lwz    r9, 0x1c(r1)
        l.lwz    r10, 0x20(r1)
        l.lwz    r11, 0x24(r1)
        l.lwz    r12, 0x28(r1)
        l.lwz    r13, 0x2c(r1)
        l.lwz    r14, 0x30(r1)
        l.lwz    r15, 0x34(r1)
        l.lwz    r16, 0x38(r1)
        l.lwz    r17, 0x3c(r1)
        l.lwz    r18, 0x40(r1)
        l.lwz    r19, 0x44(r1)
        l.lwz    r20, 0x48(r1)
        l.lwz    r21, 0x4c(r1)
        l.lwz    r22, 0x50(r1)
        l.lwz    r23, 0x54(r1)
        l.lwz    r24, 0x58(r1)
        l.lwz    r25, 0x5c(r1)
        l.lwz    r26, 0x60(r1)
        l.lwz    r27, 0x64(r1)
        l.lwz    r28, 0x68(r1)
        l.lwz    r29, 0x6c(r1)
        l.lwz    r30, 0x70(r1)
        l.lwz    r31, 0x74(r1)
        l.lwz    r32, 0x78(r1)
 
        l.addi  r1, r1, EXCEPTION_STACK_SIZE
 
        l.rfe
        l.nop
 

Line No.	Rev	Author	Line
1	349	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`/* ======================================================= [ macros ] === */`
5
6	470	julius	`#define REDZONE 128`
7			`#define EXCEPTION_STACK_SIZE (128 + REDZONE)`
8
9	349	julius	`#define CLEAR_GPR(gpr) \`
10			`l.or gpr, r0, r0`
11
12			`#define ENTRY(symbol) \`
13			`.global symbol ; \`
14			`symbol:`
15
16			`#define LOAD_SYMBOL_2_GPR(gpr,symbol) \`
17			`.global symbol ; \`
18			`l.movhi gpr, hi(symbol) ; \`
19			`l.ori gpr, gpr, lo(symbol)`
20
21			`// Really goes to configurable interrupt handler`
22	470	julius	`#define EXCEPTION_HANDLER \`
23			`l.addi r1, r1, -EXCEPTION_STACK_SIZE; \`
24	349	julius	`l.sw 4(r1), r3; \`
25			`l.sw 8(r1), r4; \`
26			`l.mfspr r3,r0,SPR_NPC; \`
27			`l.mfspr r4,r0,SPR_EPCR_BASE; \`
28			`l.j default_exception_handler; \`
29			`l.nop`
30
31			`/* =================================================== [ exceptions ] === */`
32			`.section .vectors, "ax"`
33
34
35			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
36			`.org 0x100`
37			`l.movhi r0, 0`
38	485	julius	`l.movhi r1, 0`
39			`l.movhi r2, 0`
40			`l.movhi r3, 0`
41			`l.movhi r4, 0`
42			`l.movhi r5, 0`
43			`l.movhi r6, 0`
44			`l.movhi r7, 0`
45			`l.movhi r8, 0`
46			`l.movhi r9, 0`
47			`l.movhi r10, 0`
48			`l.movhi r11, 0`
49			`l.movhi r12, 0`
50			`l.movhi r13, 0`
51			`l.movhi r14, 0`
52			`l.movhi r15, 0`
53			`l.movhi r16, 0`
54			`l.movhi r17, 0`
55			`l.movhi r18, 0`
56			`l.movhi r19, 0`
57			`l.movhi r20, 0`
58			`l.movhi r21, 0`
59			`l.movhi r22, 0`
60			`l.movhi r23, 0`
61			`l.movhi r24, 0`
62			`l.movhi r25, 0`
63			`l.movhi r26, 0`
64			`l.movhi r27, 0`
65			`l.movhi r28, 0`
66			`l.movhi r29, 0`
67			`l.movhi r30, 0`
68			`l.movhi r31, 0`
69	349	julius	`/* Clear status register, set supervisor mode */`
70			`l.ori r1, r0, SPR_SR_SM`
71			`l.mtspr r0, r1, SPR_SR`
72			`/* Clear timer */`
73			`l.mtspr r0, r0, SPR_TTMR`
74			`/* Early Stack initilization */`
75			`LOAD_SYMBOL_2_GPR(r1, _stack)`
76			`l.addi r2, r0, -3`
77			`l.and r1, r1, r2`
78
79			`/* Jump to program initialisation code */`
80			`LOAD_SYMBOL_2_GPR(r4, _start)`
81			`l.jr r4`
82			`l.nop`
83
84			`/* ---[ 0x200: BUS exception ]------------------------------------------- */`
85			`.org 0x200`
86	470	julius	`EXCEPTION_HANDLER`
87	349	julius
88			`/* ---[ 0x300: Data Page Fault exception ]------------------------------- */`
89			`.org 0x300`
90	470	julius	`EXCEPTION_HANDLER`
91	349	julius
92			`/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */`
93			`.org 0x400`
94	470	julius	`EXCEPTION_HANDLER`
95	349	julius
96	354	julius
97	349	julius	`/* ---[ 0x500: Timer exception ]----------------------------------------- */`
98			`.org 0x500`
99	354	julius	`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
100	470	julius	`//EXCEPTION_HANDLER`
101	354	julius	`/* Simply load timer_ticks variable and increment */`
102	373	julius	`.extern timer_ticks`
103	425	julius	`l.addi r1, r1, -136`
104	354	julius	`l.sw 0(r1), r25`
105			`l.sw 4(r1), r26`
106	373	julius	`l.movhi r25, hi(timer_ticks)`
107			`l.ori r25, r25, lo(timer_ticks)`
108	354	julius	`l.lwz r26, 0(r25) /* Load variable addr.*/`
109			`l.addi r26, r26, 1 /* Increment variable */`
110			`l.sw 0(r25), r26 /* Store variable */`
111			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
112			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
113			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
114			`l.lwz r25, 0(r1)`
115			`l.lwz r26, 4(r1)`
116	425	julius	`l.addi r1, r1, 136`
117	354	julius	`l.rfe`
118	349	julius
119			`/* ---[ 0x600: Aligment exception ]-------------------------------------- */`
120			`.org 0x600`
121	470	julius	`EXCEPTION_HANDLER`
122	349	julius
123			`/* ---[ 0x700: Illegal insn exception ]---------------------------------- */`
124			`.org 0x700`
125	470	julius	`EXCEPTION_HANDLER`
126	349	julius
127			`/* ---[ 0x800: External interrupt exception ]---------------------------- */`
128			`.org 0x800`
129	470	julius	`EXCEPTION_HANDLER`
130	349	julius
131			`/* ---[ 0x900: DTLB miss exception ]------------------------------------- */`
132			`.org 0x900`
133	470	julius	`EXCEPTION_HANDLER`
134	349	julius
135			`/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */`
136			`.org 0xa00`
137	470	julius	`EXCEPTION_HANDLER`
138
139	349	julius	`/* ---[ 0xb00: Range exception ]----------------------------------------- */`
140			`.org 0xb00`
141	470	julius	`EXCEPTION_HANDLER`
142	349	julius
143			`/* ---[ 0xc00: Syscall exception ]--------------------------------------- */`
144			`.org 0xc00`
145	470	julius	`EXCEPTION_HANDLER`
146	349	julius
147	470	julius	`/* ---[ 0xd00: FPU exception ]------------------------------------------- */`
148	349	julius	`.org 0xd00`
149	470	julius	`EXCEPTION_HANDLER`
150	349	julius
151			`/* ---[ 0xe00: Trap exception ]------------------------------------------ */`
152			`.org 0xe00`
153	470	julius	`EXCEPTION_HANDLER`
154	349	julius
155	470	julius	`/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */`
156			`/*`
157	349	julius	`.org 0xf00`
158	470	julius	`EXCEPTION_HANDLER`
159
160	349	julius	`.org 0x1000`
161	470	julius	`EXCEPTION_HANDLER`
162	349	julius
163			`.org 0x1100`
164	470	julius	`EXCEPTION_HANDLER`
165	349	julius
166			`.org 0x1200`
167	470	julius	`EXCEPTION_HANDLER`
168	349	julius
169			`.org 0x1300`
170	470	julius	`EXCEPTION_HANDLER`
171	349	julius
172			`.org 0x1400`
173	470	julius	`EXCEPTION_HANDLER`
174	349	julius
175	470	julius	`*/`
176			`/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */`
177			`/*`
178	349	julius	`.org 0x1500`
179	470	julius	`EXCEPTION_HANDLER`
180	349	julius
181			`.org 0x1600`
182	470	julius	`EXCEPTION_HANDLER`
183	349	julius
184			`.org 0x1700`
185	470	julius	`EXCEPTION_HANDLER`
186	349	julius
187			`.org 0x1800`
188	470	julius	`EXCEPTION_HANDLER`
189			`*/`
190			`/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */`
191			`/*`
192	349	julius	`.org 0x1900`
193	470	julius	`EXCEPTION_HANDLER`
194	349	julius
195			`.org 0x1a00`
196	470	julius	`EXCEPTION_HANDLER`
197	349	julius
198			`.org 0x1b00`
199	470	julius	`EXCEPTION_HANDLER`
200	349	julius
201			`.org 0x1c00`
202	470	julius	`EXCEPTION_HANDLER`
203	349	julius
204			`.org 0x1d00`
205	470	julius	`EXCEPTION_HANDLER`
206	349	julius
207			`.org 0x1e00`
208	470	julius	`EXCEPTION_HANDLER`
209	349	julius
210			`.org 0x1f00`
211	470	julius	`EXCEPTION_HANDLER`
212	349	julius	`*/`
213
214			`/* ========================================================= [ entry ] === */`
215			`.section .text`
216
217			`ENTRY(_start)`
218
219			`/* Instruction cache enable */`
220			`/* Check if IC present and skip enabling otherwise */`
221			`l.mfspr r24,r0,SPR_UPR`
222			`l.andi r26,r24,SPR_UPR_ICP`
223			`l.sfeq r26,r0`
224			`l.bf .L8`
225			`l.nop`
226
227			`/* Disable IC */`
228			`l.mfspr r6,r0,SPR_SR`
229			`l.addi r5,r0,-1`
230			`l.xori r5,r5,SPR_SR_ICE`
231			`l.and r5,r6,r5`
232			`l.mtspr r0,r5,SPR_SR`
233
234			`/* Establish cache block size`
235			`If BS=0, 16;`
236			`If BS=1, 32;`
237			`r14 contain block size`
238			`*/`
239			`l.mfspr r24,r0,SPR_ICCFGR`
240			`l.andi r26,r24,SPR_ICCFGR_CBS`
241			`l.srli r28,r26,7`
242			`l.ori r30,r0,16`
243			`l.sll r14,r30,r28`
244
245			`/* Establish number of cache sets`
246			`r16 contains number of cache sets`
247			`r28 contains log(# of cache sets)`
248			`*/`
249			`l.andi r26,r24,SPR_ICCFGR_NCS`
250			`l.srli r28,r26,3`
251			`l.ori r30,r0,1`
252			`l.sll r16,r30,r28`
253
254			`/* Invalidate IC */`
255			`l.addi r6,r0,0`
256			`l.sll r5,r14,r28`
257
258			`.L7:`
259			`l.mtspr r0,r6,SPR_ICBIR`
260			`l.sfne r6,r5`
261			`l.bf .L7`
262			`l.add r6,r6,r14`
263
264			`/* Enable IC */`
265			`l.mfspr r6,r0,SPR_SR`
266			`l.ori r6,r6,SPR_SR_ICE`
267			`l.mtspr r0,r6,SPR_SR`
268			`l.nop`
269			`l.nop`
270			`l.nop`
271			`l.nop`
272			`l.nop`
273			`l.nop`
274			`l.nop`
275			`l.nop`
276
277			`.L8:`
278			`/* Data cache enable */`
279			`/* Check if DC present and skip enabling otherwise */`
280			`l.mfspr r24,r0,SPR_UPR`
281			`l.andi r26,r24,SPR_UPR_DCP`
282			`l.sfeq r26,r0`
283			`l.bf .L10`
284			`l.nop`
285			`/* Disable DC */`
286			`l.mfspr r6,r0,SPR_SR`
287			`l.addi r5,r0,-1`
288			`l.xori r5,r5,SPR_SR_DCE`
289			`l.and r5,r6,r5`
290			`l.mtspr r0,r5,SPR_SR`
291			`/* Establish cache block size`
292			`If BS=0, 16;`
293			`If BS=1, 32;`
294			`r14 contain block size`
295			`*/`
296			`l.mfspr r24,r0,SPR_DCCFGR`
297			`l.andi r26,r24,SPR_DCCFGR_CBS`
298			`l.srli r28,r26,7`
299			`l.ori r30,r0,16`
300			`l.sll r14,r30,r28`
301			`/* Establish number of cache sets`
302			`r16 contains number of cache sets`
303			`r28 contains log(# of cache sets)`
304			`*/`
305			`l.andi r26,r24,SPR_DCCFGR_NCS`
306			`l.srli r28,r26,3`
307			`l.ori r30,r0,1`
308			`l.sll r16,r30,r28`
309			`/* Invalidate DC */`
310			`l.addi r6,r0,0`
311			`l.sll r5,r14,r28`
312			`.L9:`
313			`l.mtspr r0,r6,SPR_DCBIR`
314			`l.sfne r6,r5`
315			`l.bf .L9`
316			`l.add r6,r6,r14`
317			`/* Enable DC */`
318			`l.mfspr r6,r0,SPR_SR`
319			`l.ori r6,r6,SPR_SR_DCE`
320			`l.mtspr r0,r6,SPR_SR`
321
322			`.L10:`
323
324			`/* Clear BSS */`
325	475	julius	`LOAD_SYMBOL_2_GPR(r28, _bss_start)`
326			`LOAD_SYMBOL_2_GPR(r30, _bss_end)`
327	349	julius	`1:`
328			`l.sw (0)(r28), r0`
329			`l.sfltu r28, r30`
330			`l.bf 1b`
331			`l.addi r28, r28, 4`
332
333			`/* Initialise UART in a C function */`
334			`/*l.jal _uart_init`
335			`l.nop*/`
336
337			`/* Jump to main program entry point (argc = argv = 0) */`
338			`CLEAR_GPR(r3)`
339			`CLEAR_GPR(r4)`
340	373	julius	`l.jal main`
341	349	julius	`l.nop`
342
343			`/* If program exits, call exit routine */`
344			`l.addi r3, r11, 0`
345	373	julius	`l.jal exit`
346	349	julius	`l.nop`
347
348
349			`/* ====================================== [ default exception handler ] === */`
350
351			`default_exception_handler:`
352			`l.sw 0x00(r1), r2`
353			`l.sw 0x0c(r1), r5`
354			`l.sw 0x10(r1), r6`
355			`l.sw 0x14(r1), r7`
356			`l.sw 0x18(r1), r8`
357			`l.sw 0x1c(r1), r9`
358			`l.sw 0x20(r1), r10`
359			`l.sw 0x24(r1), r11`
360			`l.sw 0x28(r1), r12`
361			`l.sw 0x2c(r1), r13`
362			`l.sw 0x30(r1), r14`
363			`l.sw 0x34(r1), r15`
364			`l.sw 0x38(r1), r16`
365			`l.sw 0x3c(r1), r17`
366			`l.sw 0x40(r1), r18`
367			`l.sw 0x44(r1), r19`
368			`l.sw 0x48(r1), r20`
369			`l.sw 0x4c(r1), r21`
370			`l.sw 0x50(r1), r22`
371			`l.sw 0x54(r1), r23`
372			`l.sw 0x58(r1), r24`
373			`l.sw 0x5c(r1), r25`
374			`l.sw 0x60(r1), r26`
375			`l.sw 0x64(r1), r27`
376			`l.sw 0x68(r1), r28`
377			`l.sw 0x6c(r1), r29`
378			`l.sw 0x70(r1), r30`
379			`l.sw 0x74(r1), r31`
380			`l.sw 0x78(r1), r32`
381
382	373	julius	`l.jal default_exception_handler_c`
383	349	julius	`l.nop`
384
385			`l.lwz r2, 0x00(r1)`
386			`l.lwz r3, 0x04(r1)`
387			`l.lwz r4, 0x08(r1)`
388			`l.lwz r5, 0x0c(r1)`
389			`l.lwz r6, 0x10(r1)`
390			`l.lwz r7, 0x14(r1)`
391			`l.lwz r8, 0x18(r1)`
392			`l.lwz r9, 0x1c(r1)`
393			`l.lwz r10, 0x20(r1)`
394			`l.lwz r11, 0x24(r1)`
395			`l.lwz r12, 0x28(r1)`
396			`l.lwz r13, 0x2c(r1)`
397			`l.lwz r14, 0x30(r1)`
398			`l.lwz r15, 0x34(r1)`
399			`l.lwz r16, 0x38(r1)`
400			`l.lwz r17, 0x3c(r1)`
401			`l.lwz r18, 0x40(r1)`
402			`l.lwz r19, 0x44(r1)`
403			`l.lwz r20, 0x48(r1)`
404			`l.lwz r21, 0x4c(r1)`
405			`l.lwz r22, 0x50(r1)`
406			`l.lwz r23, 0x54(r1)`
407			`l.lwz r24, 0x58(r1)`
408			`l.lwz r25, 0x5c(r1)`
409			`l.lwz r26, 0x60(r1)`
410			`l.lwz r27, 0x64(r1)`
411			`l.lwz r28, 0x68(r1)`
412			`l.lwz r29, 0x6c(r1)`
413			`l.lwz r30, 0x70(r1)`
414			`l.lwz r31, 0x74(r1)`
415			`l.lwz r32, 0x78(r1)`
416
417	470	julius	`l.addi r1, r1, EXCEPTION_STACK_SIZE`
418	349	julius
419			`l.rfe`
420			`l.nop`
421

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