URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Blame information for rev 437

Go to most recent revision | Details | Compare with Previous | View Log


#include "spr-defs.h"
#include "board.h"
 
/* ======================================================= [ macros ] === */
 
 
#define CLEAR_GPR(gpr) \
        l.or    gpr, r0, r0
 
#define ENTRY(symbol)    \
        .global symbol ; \
symbol:
 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)  \
        .global symbol ;               \
        l.movhi gpr, hi(symbol) ;      \
        l.ori   gpr, gpr, lo(symbol)
 
        // Really goes to configurable interrupt handler
#define UNHANDLED_EXCEPTION            \
        l.addi  r1, r1, -256;          \
        l.sw    4(r1), r3;             \
        l.sw    8(r1), r4;             \
        l.mfspr r3,r0,SPR_NPC;          \
        l.mfspr r4,r0,SPR_EPCR_BASE;   \
        l.j default_exception_handler; \
        l.nop
 
 
 
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Early Stack initilization */
        LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
 
        /* Jump to program initialisation code */
        LOAD_SYMBOL_2_GPR(r4, _start)
        l.jr    r4
        l.nop
 
/* ---[ 0x200: BUS exception ]------------------------------------------- */
        .org 0x200
        UNHANDLED_EXCEPTION
 
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
        .org 0x300
        UNHANDLED_EXCEPTION
 
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
        .org 0x400
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0x500: Timer exception ]----------------------------------------- */
        .org 0x500
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        //UNHANDLED_EXCEPTION
        /* Simply load timer_ticks variable and increment */
        .extern timer_ticks
        l.addi  r1, r1, -136
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(timer_ticks)
        l.ori   r25, r25, lo(timer_ticks)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 136
        l.rfe
 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
        .org 0x600
        UNHANDLED_EXCEPTION
 
/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
        .org 0x700
        UNHANDLED_EXCEPTION
 
/* ---[ 0x800: External interrupt exception ]---------------------------- */
        .org 0x800
        UNHANDLED_EXCEPTION
 
/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
        .org 0x900
        UNHANDLED_EXCEPTION
 
/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
        .org 0xa00
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0xb00: Range exception ]----------------------------------------- */
        .org 0xb00
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
        .org 0xc00
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0xd00: Trap exception ]------------------------------------------ */
        .org 0xd00
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0xe00: Trap exception ]------------------------------------------ */
        .org 0xe00
        UNHANDLED_EXCEPTION
 
 
/* ---[ 0xf00: Reserved exceptions ]------------------------------------- */
        .org 0xf00
        UNHANDLED_EXCEPTION
/*
        .org 0x1000
        UNHANDLED_EXCEPTION
 
        .org 0x1100
        UNHANDLED_EXCEPTION
 
        .org 0x1200
        UNHANDLED_EXCEPTION
 
        .org 0x1300
        UNHANDLED_EXCEPTION
 
        .org 0x1400
        UNHANDLED_EXCEPTION
 
        .org 0x1500
        UNHANDLED_EXCEPTION
 
        .org 0x1600
        UNHANDLED_EXCEPTION
 
        .org 0x1700
        UNHANDLED_EXCEPTION
 
        .org 0x1800
        UNHANDLED_EXCEPTION
 
        .org 0x1900
        UNHANDLED_EXCEPTION
 
        .org 0x1a00
        UNHANDLED_EXCEPTION
 
        .org 0x1b00
        UNHANDLED_EXCEPTION
 
        .org 0x1c00
        UNHANDLED_EXCEPTION
 
        .org 0x1d00
        UNHANDLED_EXCEPTION
 
        .org 0x1e00
        UNHANDLED_EXCEPTION
 
        .org 0x1f00
        UNHANDLED_EXCEPTION
*/
 
/* ========================================================= [ entry ] === */
        .section .text
 
ENTRY(_start)
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
 
        /* Initialise stack */
/*      LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
*/
        /* Clear BSS */
        LOAD_SYMBOL_2_GPR(r28, ___bss_start)
        LOAD_SYMBOL_2_GPR(r30, __end)
1:
        l.sw    (0)(r28), r0
        l.sfltu r28, r30
        l.bf    1b
        l.addi  r28, r28, 4
 
 
        /* Initialise UART in a C function */
        /*l.jal    _uart_init
        l.nop*/
 
 
        /* Jump to main program entry point (argc = argv = 0) */
        CLEAR_GPR(r3)
        CLEAR_GPR(r4)
        l.jal   main
        l.nop
 
        /* If program exits, call exit routine */
        l.addi  r3, r11, 0
        l.jal   exit
        l.nop
 
 
/* ====================================== [ default exception handler ] === */
 
default_exception_handler:
        l.sw    0x00(r1), r2
        l.sw    0x0c(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
        l.sw    0x78(r1), r32
 
        l.jal   default_exception_handler_c
        l.nop
 
        l.lwz    r2, 0x00(r1)
        l.lwz    r3, 0x04(r1)
        l.lwz    r4, 0x08(r1)
        l.lwz    r5, 0x0c(r1)
        l.lwz    r6, 0x10(r1)
        l.lwz    r7, 0x14(r1)
        l.lwz    r8, 0x18(r1)
        l.lwz    r9, 0x1c(r1)
        l.lwz    r10, 0x20(r1)
        l.lwz    r11, 0x24(r1)
        l.lwz    r12, 0x28(r1)
        l.lwz    r13, 0x2c(r1)
        l.lwz    r14, 0x30(r1)
        l.lwz    r15, 0x34(r1)
        l.lwz    r16, 0x38(r1)
        l.lwz    r17, 0x3c(r1)
        l.lwz    r18, 0x40(r1)
        l.lwz    r19, 0x44(r1)
        l.lwz    r20, 0x48(r1)
        l.lwz    r21, 0x4c(r1)
        l.lwz    r22, 0x50(r1)
        l.lwz    r23, 0x54(r1)
        l.lwz    r24, 0x58(r1)
        l.lwz    r25, 0x5c(r1)
        l.lwz    r26, 0x60(r1)
        l.lwz    r27, 0x64(r1)
        l.lwz    r28, 0x68(r1)
        l.lwz    r29, 0x6c(r1)
        l.lwz    r30, 0x70(r1)
        l.lwz    r31, 0x74(r1)
        l.lwz    r32, 0x78(r1)
 
        l.addi  r1, r1, 256
 
        l.rfe
        l.nop
 

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Blame information for rev 437

Line No.	Rev	Author	Line
1	349	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`/* ======================================================= [ macros ] === */`
5
6
7			`#define CLEAR_GPR(gpr) \`
8			`l.or gpr, r0, r0`
9
10			`#define ENTRY(symbol) \`
11			`.global symbol ; \`
12			`symbol:`
13
14			`#define LOAD_SYMBOL_2_GPR(gpr,symbol) \`
15			`.global symbol ; \`
16			`l.movhi gpr, hi(symbol) ; \`
17			`l.ori gpr, gpr, lo(symbol)`
18
19			`// Really goes to configurable interrupt handler`
20			`#define UNHANDLED_EXCEPTION \`
21	425	julius	`l.addi r1, r1, -256; \`
22	349	julius	`l.sw 4(r1), r3; \`
23			`l.sw 8(r1), r4; \`
24			`l.mfspr r3,r0,SPR_NPC; \`
25			`l.mfspr r4,r0,SPR_EPCR_BASE; \`
26			`l.j default_exception_handler; \`
27			`l.nop`
28
29
30
31
32
33			`/* =================================================== [ exceptions ] === */`
34			`.section .vectors, "ax"`
35
36
37			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
38			`.org 0x100`
39			`l.movhi r0, 0`
40			`/* Clear status register, set supervisor mode */`
41			`l.ori r1, r0, SPR_SR_SM`
42			`l.mtspr r0, r1, SPR_SR`
43			`/* Clear timer */`
44			`l.mtspr r0, r0, SPR_TTMR`
45			`/* Early Stack initilization */`
46			`LOAD_SYMBOL_2_GPR(r1, _stack)`
47			`l.addi r2, r0, -3`
48			`l.and r1, r1, r2`
49
50			`/* Jump to program initialisation code */`
51			`LOAD_SYMBOL_2_GPR(r4, _start)`
52			`l.jr r4`
53			`l.nop`
54
55			`/* ---[ 0x200: BUS exception ]------------------------------------------- */`
56			`.org 0x200`
57			`UNHANDLED_EXCEPTION`
58
59			`/* ---[ 0x300: Data Page Fault exception ]------------------------------- */`
60			`.org 0x300`
61			`UNHANDLED_EXCEPTION`
62
63			`/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */`
64			`.org 0x400`
65			`UNHANDLED_EXCEPTION`
66
67	354	julius
68	349	julius	`/* ---[ 0x500: Timer exception ]----------------------------------------- */`
69			`.org 0x500`
70	354	julius	`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
71			`//UNHANDLED_EXCEPTION`
72			`/* Simply load timer_ticks variable and increment */`
73	373	julius	`.extern timer_ticks`
74	425	julius	`l.addi r1, r1, -136`
75	354	julius	`l.sw 0(r1), r25`
76			`l.sw 4(r1), r26`
77	373	julius	`l.movhi r25, hi(timer_ticks)`
78			`l.ori r25, r25, lo(timer_ticks)`
79	354	julius	`l.lwz r26, 0(r25) /* Load variable addr.*/`
80			`l.addi r26, r26, 1 /* Increment variable */`
81			`l.sw 0(r25), r26 /* Store variable */`
82			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
83			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
84			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
85			`l.lwz r25, 0(r1)`
86			`l.lwz r26, 4(r1)`
87	425	julius	`l.addi r1, r1, 136`
88	354	julius	`l.rfe`
89	349	julius
90			`/* ---[ 0x600: Aligment exception ]-------------------------------------- */`
91			`.org 0x600`
92			`UNHANDLED_EXCEPTION`
93
94			`/* ---[ 0x700: Illegal insn exception ]---------------------------------- */`
95			`.org 0x700`
96			`UNHANDLED_EXCEPTION`
97
98			`/* ---[ 0x800: External interrupt exception ]---------------------------- */`
99			`.org 0x800`
100			`UNHANDLED_EXCEPTION`
101
102			`/* ---[ 0x900: DTLB miss exception ]------------------------------------- */`
103			`.org 0x900`
104			`UNHANDLED_EXCEPTION`
105
106			`/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */`
107			`.org 0xa00`
108			`UNHANDLED_EXCEPTION`
109
110
111			`/* ---[ 0xb00: Range exception ]----------------------------------------- */`
112			`.org 0xb00`
113			`UNHANDLED_EXCEPTION`
114
115
116			`/* ---[ 0xc00: Syscall exception ]--------------------------------------- */`
117			`.org 0xc00`
118			`UNHANDLED_EXCEPTION`
119
120
121			`/* ---[ 0xd00: Trap exception ]------------------------------------------ */`
122			`.org 0xd00`
123			`UNHANDLED_EXCEPTION`
124
125
126			`/* ---[ 0xe00: Trap exception ]------------------------------------------ */`
127			`.org 0xe00`
128			`UNHANDLED_EXCEPTION`
129
130
131			`/* ---[ 0xf00: Reserved exceptions ]------------------------------------- */`
132			`.org 0xf00`
133			`UNHANDLED_EXCEPTION`
134			`/*`
135			`.org 0x1000`
136			`UNHANDLED_EXCEPTION`
137
138			`.org 0x1100`
139			`UNHANDLED_EXCEPTION`
140
141			`.org 0x1200`
142			`UNHANDLED_EXCEPTION`
143
144			`.org 0x1300`
145			`UNHANDLED_EXCEPTION`
146
147			`.org 0x1400`
148			`UNHANDLED_EXCEPTION`
149
150			`.org 0x1500`
151			`UNHANDLED_EXCEPTION`
152
153			`.org 0x1600`
154			`UNHANDLED_EXCEPTION`
155
156			`.org 0x1700`
157			`UNHANDLED_EXCEPTION`
158
159			`.org 0x1800`
160			`UNHANDLED_EXCEPTION`
161
162			`.org 0x1900`
163			`UNHANDLED_EXCEPTION`
164
165			`.org 0x1a00`
166			`UNHANDLED_EXCEPTION`
167
168			`.org 0x1b00`
169			`UNHANDLED_EXCEPTION`
170
171			`.org 0x1c00`
172			`UNHANDLED_EXCEPTION`
173
174			`.org 0x1d00`
175			`UNHANDLED_EXCEPTION`
176
177			`.org 0x1e00`
178			`UNHANDLED_EXCEPTION`
179
180			`.org 0x1f00`
181			`UNHANDLED_EXCEPTION`
182			`*/`
183
184			`/* ========================================================= [ entry ] === */`
185			`.section .text`
186
187			`ENTRY(_start)`
188
189			`/* Instruction cache enable */`
190			`/* Check if IC present and skip enabling otherwise */`
191			`l.mfspr r24,r0,SPR_UPR`
192			`l.andi r26,r24,SPR_UPR_ICP`
193			`l.sfeq r26,r0`
194			`l.bf .L8`
195			`l.nop`
196
197			`/* Disable IC */`
198			`l.mfspr r6,r0,SPR_SR`
199			`l.addi r5,r0,-1`
200			`l.xori r5,r5,SPR_SR_ICE`
201			`l.and r5,r6,r5`
202			`l.mtspr r0,r5,SPR_SR`
203
204			`/* Establish cache block size`
205			`If BS=0, 16;`
206			`If BS=1, 32;`
207			`r14 contain block size`
208			`*/`
209			`l.mfspr r24,r0,SPR_ICCFGR`
210			`l.andi r26,r24,SPR_ICCFGR_CBS`
211			`l.srli r28,r26,7`
212			`l.ori r30,r0,16`
213			`l.sll r14,r30,r28`
214
215			`/* Establish number of cache sets`
216			`r16 contains number of cache sets`
217			`r28 contains log(# of cache sets)`
218			`*/`
219			`l.andi r26,r24,SPR_ICCFGR_NCS`
220			`l.srli r28,r26,3`
221			`l.ori r30,r0,1`
222			`l.sll r16,r30,r28`
223
224			`/* Invalidate IC */`
225			`l.addi r6,r0,0`
226			`l.sll r5,r14,r28`
227
228			`.L7:`
229			`l.mtspr r0,r6,SPR_ICBIR`
230			`l.sfne r6,r5`
231			`l.bf .L7`
232			`l.add r6,r6,r14`
233
234			`/* Enable IC */`
235			`l.mfspr r6,r0,SPR_SR`
236			`l.ori r6,r6,SPR_SR_ICE`
237			`l.mtspr r0,r6,SPR_SR`
238			`l.nop`
239			`l.nop`
240			`l.nop`
241			`l.nop`
242			`l.nop`
243			`l.nop`
244			`l.nop`
245			`l.nop`
246
247			`.L8:`
248			`/* Data cache enable */`
249			`/* Check if DC present and skip enabling otherwise */`
250			`l.mfspr r24,r0,SPR_UPR`
251			`l.andi r26,r24,SPR_UPR_DCP`
252			`l.sfeq r26,r0`
253			`l.bf .L10`
254			`l.nop`
255			`/* Disable DC */`
256			`l.mfspr r6,r0,SPR_SR`
257			`l.addi r5,r0,-1`
258			`l.xori r5,r5,SPR_SR_DCE`
259			`l.and r5,r6,r5`
260			`l.mtspr r0,r5,SPR_SR`
261			`/* Establish cache block size`
262			`If BS=0, 16;`
263			`If BS=1, 32;`
264			`r14 contain block size`
265			`*/`
266			`l.mfspr r24,r0,SPR_DCCFGR`
267			`l.andi r26,r24,SPR_DCCFGR_CBS`
268			`l.srli r28,r26,7`
269			`l.ori r30,r0,16`
270			`l.sll r14,r30,r28`
271			`/* Establish number of cache sets`
272			`r16 contains number of cache sets`
273			`r28 contains log(# of cache sets)`
274			`*/`
275			`l.andi r26,r24,SPR_DCCFGR_NCS`
276			`l.srli r28,r26,3`
277			`l.ori r30,r0,1`
278			`l.sll r16,r30,r28`
279			`/* Invalidate DC */`
280			`l.addi r6,r0,0`
281			`l.sll r5,r14,r28`
282			`.L9:`
283			`l.mtspr r0,r6,SPR_DCBIR`
284			`l.sfne r6,r5`
285			`l.bf .L9`
286			`l.add r6,r6,r14`
287			`/* Enable DC */`
288			`l.mfspr r6,r0,SPR_SR`
289			`l.ori r6,r6,SPR_SR_DCE`
290			`l.mtspr r0,r6,SPR_SR`
291
292			`.L10:`
293
294			`/* Initialise stack */`
295			`/* LOAD_SYMBOL_2_GPR(r1, _stack)`
296			`l.addi r2, r0, -3`
297			`l.and r1, r1, r2`
298			`*/`
299			`/* Clear BSS */`
300			`LOAD_SYMBOL_2_GPR(r28, ___bss_start)`
301			`LOAD_SYMBOL_2_GPR(r30, __end)`
302			`1:`
303			`l.sw (0)(r28), r0`
304			`l.sfltu r28, r30`
305			`l.bf 1b`
306			`l.addi r28, r28, 4`
307
308
309			`/* Initialise UART in a C function */`
310			`/*l.jal _uart_init`
311			`l.nop*/`
312
313
314			`/* Jump to main program entry point (argc = argv = 0) */`
315			`CLEAR_GPR(r3)`
316			`CLEAR_GPR(r4)`
317	373	julius	`l.jal main`
318	349	julius	`l.nop`
319
320			`/* If program exits, call exit routine */`
321			`l.addi r3, r11, 0`
322	373	julius	`l.jal exit`
323	349	julius	`l.nop`
324
325
326			`/* ====================================== [ default exception handler ] === */`
327
328			`default_exception_handler:`
329			`l.sw 0x00(r1), r2`
330			`l.sw 0x0c(r1), r5`
331			`l.sw 0x10(r1), r6`
332			`l.sw 0x14(r1), r7`
333			`l.sw 0x18(r1), r8`
334			`l.sw 0x1c(r1), r9`
335			`l.sw 0x20(r1), r10`
336			`l.sw 0x24(r1), r11`
337			`l.sw 0x28(r1), r12`
338			`l.sw 0x2c(r1), r13`
339			`l.sw 0x30(r1), r14`
340			`l.sw 0x34(r1), r15`
341			`l.sw 0x38(r1), r16`
342			`l.sw 0x3c(r1), r17`
343			`l.sw 0x40(r1), r18`
344			`l.sw 0x44(r1), r19`
345			`l.sw 0x48(r1), r20`
346			`l.sw 0x4c(r1), r21`
347			`l.sw 0x50(r1), r22`
348			`l.sw 0x54(r1), r23`
349			`l.sw 0x58(r1), r24`
350			`l.sw 0x5c(r1), r25`
351			`l.sw 0x60(r1), r26`
352			`l.sw 0x64(r1), r27`
353			`l.sw 0x68(r1), r28`
354			`l.sw 0x6c(r1), r29`
355			`l.sw 0x70(r1), r30`
356			`l.sw 0x74(r1), r31`
357			`l.sw 0x78(r1), r32`
358
359	373	julius	`l.jal default_exception_handler_c`
360	349	julius	`l.nop`
361
362			`l.lwz r2, 0x00(r1)`
363			`l.lwz r3, 0x04(r1)`
364			`l.lwz r4, 0x08(r1)`
365			`l.lwz r5, 0x0c(r1)`
366			`l.lwz r6, 0x10(r1)`
367			`l.lwz r7, 0x14(r1)`
368			`l.lwz r8, 0x18(r1)`
369			`l.lwz r9, 0x1c(r1)`
370			`l.lwz r10, 0x20(r1)`
371			`l.lwz r11, 0x24(r1)`
372			`l.lwz r12, 0x28(r1)`
373			`l.lwz r13, 0x2c(r1)`
374			`l.lwz r14, 0x30(r1)`
375			`l.lwz r15, 0x34(r1)`
376			`l.lwz r16, 0x38(r1)`
377			`l.lwz r17, 0x3c(r1)`
378			`l.lwz r18, 0x40(r1)`
379			`l.lwz r19, 0x44(r1)`
380			`l.lwz r20, 0x48(r1)`
381			`l.lwz r21, 0x4c(r1)`
382			`l.lwz r22, 0x50(r1)`
383			`l.lwz r23, 0x54(r1)`
384			`l.lwz r24, 0x58(r1)`
385			`l.lwz r25, 0x5c(r1)`
386			`l.lwz r26, 0x60(r1)`
387			`l.lwz r27, 0x64(r1)`
388			`l.lwz r28, 0x68(r1)`
389			`l.lwz r29, 0x6c(r1)`
390			`l.lwz r30, 0x70(r1)`
391			`l.lwz r31, 0x74(r1)`
392			`l.lwz r32, 0x78(r1)`
393
394	425	julius	`l.addi r1, r1, 256`
395	349	julius
396			`l.rfe`
397			`l.nop`
398