OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [int.c] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 486 julius
/*
2
 *
3
 * User interrupt handler software for OR1200
4
 *
5
 */
6 349 julius
 
7 393 julius
#include "or1200-utils.h"
8 349 julius
#include "spr-defs.h"
9
#include "int.h"
10
 
11
/* Interrupt handlers table */
12
struct ihnd int_handlers[MAX_INT_HANDLERS];
13
 
14
/* Initialize routine */
15
int int_init()
16
{
17
  int i;
18
 
19
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
20
    int_handlers[i].handler = 0;
21
    int_handlers[i].arg = 0;
22
  }
23
 
24
  return 0;
25
}
26
 
27
/* Add interrupt handler */
28 530 julius
int int_add(unsigned long irq, void (* handler)(void *), void *arg)
29 349 julius
{
30 530 julius
  if(irq >= MAX_INT_HANDLERS)
31 349 julius
    return -1;
32
 
33 530 julius
  int_handlers[irq].handler = handler;
34
  int_handlers[irq].arg = arg;
35 349 julius
 
36 530 julius
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
37 349 julius
 
38
  return 0;
39
}
40
 
41
/* Disable interrupt */
42 530 julius
int int_disable(unsigned long irq)
43 349 julius
{
44 530 julius
  if(irq >= MAX_INT_HANDLERS)
45 349 julius
    return -1;
46
 
47 530 julius
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << irq));
48 349 julius
 
49
  return 0;
50
}
51
 
52
/* Enable interrupt */
53 530 julius
int int_enable(unsigned long irq)
54 349 julius
{
55 530 julius
  if(irq >= MAX_INT_HANDLERS)
56 349 julius
    return -1;
57
 
58 530 julius
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq));
59 349 julius
 
60
  return 0;
61
}
62
 
63
/* Main interrupt handler */
64
void int_main()
65
{
66
  unsigned long picsr = mfspr(SPR_PICSR);
67
  unsigned long i = 0;
68
 
69
  mtspr(SPR_PICSR, 0);
70
 
71
  while(i < 32) {
72
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
73
      (*int_handlers[i].handler)(int_handlers[i].arg);
74 530 julius
#ifdef OR1200_INT_CHECK_BIT_CLEARED
75
      // Ensure PICSR bit is cleared, incase it takes some time for the
76
      // IRQ line going low to propagate back to PIC
77
      while (mfspr(SPR_PICSR) & (0x00000001L << i))
78
#endif
79
              mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
80 349 julius
    }
81
    i++;
82
  }
83
}
84
 
85
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.