OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [int.c] - Blame information for rev 478

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius
/* This file is part of test microkernel for OpenRISC 1000. */
2
/* (C) 2001 Simon Srot, srot@opencores.org */
3
 
4 393 julius
#include "or1200-utils.h"
5 349 julius
#include "spr-defs.h"
6
#include "int.h"
7
 
8
/* Interrupt handlers table */
9
struct ihnd int_handlers[MAX_INT_HANDLERS];
10
 
11
/* Initialize routine */
12
int int_init()
13
{
14
  int i;
15
 
16
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
17
    int_handlers[i].handler = 0;
18
    int_handlers[i].arg = 0;
19
  }
20
 
21
  return 0;
22
}
23
 
24
/* Add interrupt handler */
25
int int_add(unsigned long vect, void (* handler)(void *), void *arg)
26
{
27
  if(vect >= MAX_INT_HANDLERS)
28
    return -1;
29
 
30
  int_handlers[vect].handler = handler;
31
  int_handlers[vect].arg = arg;
32
 
33
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
34
 
35
  return 0;
36
}
37
 
38
/* Disable interrupt */
39
int int_disable(unsigned long vect)
40
{
41
  if(vect >= MAX_INT_HANDLERS)
42
    return -1;
43
 
44
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
45
 
46
  return 0;
47
}
48
 
49
/* Enable interrupt */
50
int int_enable(unsigned long vect)
51
{
52
  if(vect >= MAX_INT_HANDLERS)
53
    return -1;
54
 
55
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
56
 
57
  return 0;
58
}
59
 
60
/* Main interrupt handler */
61
void int_main()
62
{
63
  unsigned long picsr = mfspr(SPR_PICSR);
64
  unsigned long i = 0;
65
 
66
  mtspr(SPR_PICSR, 0);
67
 
68
  while(i < 32) {
69
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
70
      (*int_handlers[i].handler)(int_handlers[i].arg);
71
      mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
72
    }
73
    i++;
74
  }
75
}
76
 
77
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.