OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [or1200-utils.c] - Blame information for rev 522

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius
#include "spr-defs.h"
2 393 julius
#include "or1200-utils.h"
3
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC)
4 349 julius
 
5
/* For writing into SPR. */
6 411 julius
void
7
mtspr(unsigned long spr, unsigned long value)
8 349 julius
{
9
  asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
10
}
11
 
12
/* For reading SPR. */
13 411 julius
unsigned long
14
mfspr(unsigned long spr)
15 349 julius
{
16
  unsigned long value;
17
  asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
18
  return value;
19
}
20
 
21
/* Print out a character via simulator */
22 411 julius
void
23
sim_putc(unsigned char c)
24 349 julius
{
25
  asm("l.addi\tr3,%0,0": :"r" (c));
26
  asm("l.nop %0": :"K" (NOP_PUTC));
27
}
28
 
29
/* print long */
30 411 julius
void
31
report(unsigned long value)
32 349 julius
{
33
  asm("l.addi\tr3,%0,0": :"r" (value));
34
  asm("l.nop %0": :"K" (NOP_REPORT));
35
}
36
 
37
/* Loops/exits simulation */
38 411 julius
void
39
exit (int i)
40 349 julius
{
41
  asm("l.add r3,r0,%0": : "r" (i));
42
  asm("l.nop %0": :"K" (NOP_EXIT));
43
  while (1);
44
}
45
 
46 408 julius
/* Enable user interrupts */
47
void
48
cpu_enable_user_interrupts(void)
49
{
50
  /* Enable interrupts in supervisor register */
51
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
52
}
53 349 julius
 
54
/* Tick timer variable */
55
unsigned long timer_ticks;
56
 
57
/* Tick timer functions */
58
/* Enable tick timer and interrupt generation */
59 411 julius
void
60
cpu_enable_timer(void)
61 349 julius
{
62 411 julius
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
63 349 julius
  mtspr(SPR_SR, SPR_SR_TEE | mfspr(SPR_SR));
64 411 julius
 
65 349 julius
}
66
 
67
/* Disable tick timer and interrupt generation */
68 411 julius
void
69
cpu_disable_timer(void)
70 349 julius
{
71
  // Disable timer: clear it all!
72
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_TEE);
73
  mtspr(SPR_TTMR, 0);
74
 
75
}
76
 
77
/* Timer increment - called by interrupt routine */
78 411 julius
void
79
cpu_timer_tick(void)
80 349 julius
{
81
  timer_ticks++;
82 488 julius
  // Reset timer mode register to interrupt with same interval
83
  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
84
        ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
85 349 julius
}
86
 
87
/* Reset tick counter */
88 411 julius
void
89
cpu_reset_timer_ticks(void)
90 349 julius
{
91
  timer_ticks=0;
92
}
93
 
94
/* Get tick counter */
95 411 julius
unsigned long
96
cpu_get_timer_ticks(void)
97 349 julius
{
98
  return timer_ticks;
99
}
100
 
101 505 julius
/* Wait for 10ms, assumes CLK_HZ is 100, which it usually is.
102
   Will be slightly inaccurate!*/
103 411 julius
void
104
cpu_sleep_10ms(void)
105 349 julius
{
106 505 julius
  unsigned long ttcr = mfspr(SPR_TTCR) & SPR_TTCR_PERIOD;
107 411 julius
  unsigned long first_time = cpu_get_timer_ticks();
108 505 julius
  while (first_time == cpu_get_timer_ticks()); // Wait for tick to occur
109
  // Now wait until we're past the tick value we read before to know we've
110
  // gone at least enough
111
  while(ttcr > (mfspr(SPR_TTCR) & SPR_TTCR_PERIOD));
112
 
113 349 julius
}
114
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.