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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [simple-spi/] [simple-spi.c] - Blame information for rev 411

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/*
 * Simple SPI module driver
 *
 * Julius Baxter, julius.baxter@orsoc.se
 *
 */
 
#include "board.h"
#include "simple-spi.h"
#include "cpu-utils.h"
 
const int spi_base_adr[1] = {SPI0_BASE};
 
void
spi_core_enable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_disable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_interrupt_enable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_disable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_flag_clear(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;
}
 
void
spi_core_clock_setup(int core, char polarity, char phase, char rate,
                          char ext_rate)
{
  char spcr = REG8((spi_base_adr[core] + SIMPLESPI_SPCR));
 
  if (polarity)
    spcr |= SIMPLESPI_SPCR_CPOL;
  else
    spcr &= ~SIMPLESPI_SPCR_CPOL;
 
  if (phase)
    spcr |= SIMPLESPI_SPCR_CPHA;
  else
    spcr &= ~SIMPLESPI_SPCR_CPHA;
 
  spcr = (spcr & ~SIMPLESPI_SPCR_SPR) | (rate & SIMPLESPI_SPCR_SPR);
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) = spcr;
 
  char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
 
  sper = (sper & ~SIMPLESPI_SPER_ESPR) | (ext_rate & SIMPLESPI_SPER_ESPR);
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
 
}
 
void
spi_core_set_int_count(int core, char cnt)
{
  char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
 
  sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
 
}
// slave_sel_dec is decoded (so asserted bit in right place)
void
spi_core_slave_select(int core, char slave_sel_dec)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
}
 
int
spi_core_data_avail(int core)
{
  return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);
}
 
int
spi_core_write_avail(int core)
{
  return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);
}
 
// Should call spi_core_write_avail() before calling this, we don't check
void
spi_core_write_data(int core, char data)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPDR)) = data;
}
 
char
spi_core_read_data(int core)
{
  return REG8((spi_base_adr[core] + SIMPLESPI_SPDR));
}

Line No.	Rev	Author	Line
1	374	julius	`/*`
2			`* Simple SPI module driver`
3			`*`
4			`* Julius Baxter, julius.baxter@orsoc.se`
5			`*`
6			`*/`
7
8			`#include "board.h"`
9			`#include "simple-spi.h"`
10	393	julius	`#include "cpu-utils.h"`
11	374	julius
12			`const int spi_base_adr[1] = {SPI0_BASE};`
13
14	393	julius	`void`
15			`spi_core_enable(int core)`
16	374	julius	`{`
17			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) \|= SIMPLESPI_SPCR_SPE;`
18			`}`
19
20	393	julius	`void`
21			`spi_core_disable(int core)`
22	374	julius	`{`
23			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;`
24			`}`
25
26	393	julius	`void`
27			`spi_core_interrupt_enable(int core)`
28	374	julius	`{`
29			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) \|= SIMPLESPI_SPCR_SPIE;`
30			`}`
31
32	393	julius	`void`
33			`spi_core_interrupt_disable(int core)`
34	374	julius	`{`
35			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;`
36			`}`
37
38	393	julius	`void`
39			`spi_core_interrupt_flag_clear(int core)`
40	374	julius	`{`
41			`REG8((spi_base_adr[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;`
42			`}`
43
44	393	julius	`void`
45			`spi_core_clock_setup(int core, char polarity, char phase, char rate,`
46	374	julius	`char ext_rate)`
47			`{`
48			`char spcr = REG8((spi_base_adr[core] + SIMPLESPI_SPCR));`
49
50			`if (polarity)`
51			`spcr \|= SIMPLESPI_SPCR_CPOL;`
52			`else`
53			`spcr &= ~SIMPLESPI_SPCR_CPOL;`
54
55			`if (phase)`
56			`spcr \|= SIMPLESPI_SPCR_CPHA;`
57			`else`
58			`spcr &= ~SIMPLESPI_SPCR_CPHA;`
59
60			`spcr = (spcr & ~SIMPLESPI_SPCR_SPR) \| (rate & SIMPLESPI_SPCR_SPR);`
61
62			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) = spcr;`
63
64			`char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));`
65
66			`sper = (sper & ~SIMPLESPI_SPER_ESPR) \| (ext_rate & SIMPLESPI_SPER_ESPR);`
67
68			`REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;`
69
70			`}`
71
72	393	julius	`void`
73			`spi_core_set_int_count(int core, char cnt)`
74	374	julius	`{`
75			`char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));`
76
77			`sper = (sper & ~SIMPLESPI_SPER_ICNT) \| cnt;`
78
79			`REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;`
80
81			`}`
82			`// slave_sel_dec is decoded (so asserted bit in right place)`
83	393	julius	`void`
84			`spi_core_slave_select(int core, char slave_sel_dec)`
85	374	julius	`{`
86			`REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;`
87			`}`
88
89	393	julius	`int`
90			`spi_core_data_avail(int core)`
91	374	julius	`{`
92			`return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);`
93			`}`
94
95	393	julius	`int`
96			`spi_core_write_avail(int core)`
97	374	julius	`{`
98			`return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);`
99			`}`
100
101			`// Should call spi_core_write_avail() before calling this, we don't check`
102	393	julius	`void`
103			`spi_core_write_data(int core, char data)`
104	374	julius	`{`
105			`REG8((spi_base_adr[core] + SIMPLESPI_SPDR)) = data;`
106			`}`
107
108	393	julius	`char`
109			`spi_core_read_data(int core)`
110	374	julius	`{`
111			`return REG8((spi_base_adr[core] + SIMPLESPI_SPDR));`
112			`}`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [simple-spi/] [simple-spi.c] - Blame information for rev 411