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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [simple-spi/] [simple-spi.c] - Blame information for rev 485

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/*
 * Simple SPI module driver
 *
 * Julius Baxter, julius.baxter@orsoc.se
 *
 */
 
#include "board.h"
#include "simple-spi.h"
#include "cpu-utils.h"
 
 
const int spi_base_adr[1] = {
#ifdef SPI0_BASE
        SPI0_BASE
#else
 
#endif
};
 
void
spi_core_enable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_disable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_interrupt_enable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_disable(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_flag_clear(int core)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;
}
 
void
spi_core_clock_setup(int core, char polarity, char phase, char rate,
                          char ext_rate)
{
  char spcr = REG8((spi_base_adr[core] + SIMPLESPI_SPCR));
 
  if (polarity)
    spcr |= SIMPLESPI_SPCR_CPOL;
  else
    spcr &= ~SIMPLESPI_SPCR_CPOL;
 
  if (phase)
    spcr |= SIMPLESPI_SPCR_CPHA;
  else
    spcr &= ~SIMPLESPI_SPCR_CPHA;
 
  spcr = (spcr & ~SIMPLESPI_SPCR_SPR) | (rate & SIMPLESPI_SPCR_SPR);
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) = spcr;
 
  char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
 
  sper = (sper & ~SIMPLESPI_SPER_ESPR) | (ext_rate & SIMPLESPI_SPER_ESPR);
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
 
}
 
void
spi_core_set_int_count(int core, char cnt)
{
  char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
 
  sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
 
  REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
 
}
// No decode on slave select lines, so assert correct bit to select slave
void
spi_core_slave_select(int core, char slave_sel_dec)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
}
 
int
spi_core_data_avail(int core)
{
  return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);
}
 
int
spi_core_write_avail(int core)
{
  return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);
}
 
// Should call spi_core_write_avail() before calling this, we don't check
void
spi_core_write_data(int core, char data)
{
  REG8((spi_base_adr[core] + SIMPLESPI_SPDR)) = data;
}
 
char
spi_core_read_data(int core)
{
  return REG8((spi_base_adr[core] + SIMPLESPI_SPDR));
}

Line No.	Rev	Author	Line
1	374	julius	`/*`
2			`* Simple SPI module driver`
3			`*`
4			`* Julius Baxter, julius.baxter@orsoc.se`
5			`*`
6			`*/`
7
8			`#include "board.h"`
9			`#include "simple-spi.h"`
10	393	julius	`#include "cpu-utils.h"`
11	374	julius
12
13	485	julius	`const int spi_base_adr[1] = {`
14			`#ifdef SPI0_BASE`
15			`SPI0_BASE`
16			`#else`
17
18			`#endif`
19			`};`
20
21	393	julius	`void`
22			`spi_core_enable(int core)`
23	374	julius	`{`
24			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) \|= SIMPLESPI_SPCR_SPE;`
25			`}`
26
27	393	julius	`void`
28			`spi_core_disable(int core)`
29	374	julius	`{`
30			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;`
31			`}`
32
33	393	julius	`void`
34			`spi_core_interrupt_enable(int core)`
35	374	julius	`{`
36			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) \|= SIMPLESPI_SPCR_SPIE;`
37			`}`
38
39	393	julius	`void`
40			`spi_core_interrupt_disable(int core)`
41	374	julius	`{`
42			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;`
43			`}`
44
45	393	julius	`void`
46			`spi_core_interrupt_flag_clear(int core)`
47	374	julius	`{`
48			`REG8((spi_base_adr[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;`
49			`}`
50
51	393	julius	`void`
52			`spi_core_clock_setup(int core, char polarity, char phase, char rate,`
53	374	julius	`char ext_rate)`
54			`{`
55			`char spcr = REG8((spi_base_adr[core] + SIMPLESPI_SPCR));`
56
57			`if (polarity)`
58			`spcr \|= SIMPLESPI_SPCR_CPOL;`
59			`else`
60			`spcr &= ~SIMPLESPI_SPCR_CPOL;`
61
62			`if (phase)`
63			`spcr \|= SIMPLESPI_SPCR_CPHA;`
64			`else`
65			`spcr &= ~SIMPLESPI_SPCR_CPHA;`
66
67			`spcr = (spcr & ~SIMPLESPI_SPCR_SPR) \| (rate & SIMPLESPI_SPCR_SPR);`
68
69			`REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) = spcr;`
70
71			`char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));`
72
73			`sper = (sper & ~SIMPLESPI_SPER_ESPR) \| (ext_rate & SIMPLESPI_SPER_ESPR);`
74
75			`REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;`
76
77			`}`
78
79	393	julius	`void`
80			`spi_core_set_int_count(int core, char cnt)`
81	374	julius	`{`
82			`char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));`
83
84			`sper = (sper & ~SIMPLESPI_SPER_ICNT) \| cnt;`
85
86			`REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;`
87
88			`}`
89	415	julius	`// No decode on slave select lines, so assert correct bit to select slave`
90	393	julius	`void`
91			`spi_core_slave_select(int core, char slave_sel_dec)`
92	374	julius	`{`
93			`REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;`
94			`}`
95
96	393	julius	`int`
97			`spi_core_data_avail(int core)`
98	374	julius	`{`
99			`return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);`
100			`}`
101
102	393	julius	`int`
103			`spi_core_write_avail(int core)`
104	374	julius	`{`
105			`return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);`
106			`}`
107
108			`// Should call spi_core_write_avail() before calling this, we don't check`
109	393	julius	`void`
110			`spi_core_write_data(int core, char data)`
111	374	julius	`{`
112			`REG8((spi_base_adr[core] + SIMPLESPI_SPDR)) = data;`
113			`}`
114
115	393	julius	`char`
116			`spi_core_read_data(int core)`
117	374	julius	`{`
118			`return REG8((spi_base_adr[core] + SIMPLESPI_SPDR));`
119			`}`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [simple-spi/] [simple-spi.c] - Blame information for rev 485