OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [simple-spi/] [simple-spi.c] - Blame information for rev 522

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 374 julius
/*
2
 * Simple SPI module driver
3
 *
4
 * Julius Baxter, julius.baxter@orsoc.se
5
 *
6
 */
7
 
8
#include "board.h"
9
#include "simple-spi.h"
10 393 julius
#include "cpu-utils.h"
11 374 julius
 
12 505 julius
#ifdef SPI_NUM_CORES
13
const int SPI_BASE_ADR[SPI_NUM_CORES] = {SPI_BASE_ADDRESSES_CSV};
14
#else
15
// For older builds - need to change them all over to newer format
16 485 julius
#ifdef SPI0_BASE
17 505 julius
const int SPI_BASE_ADR[1] = {SPI0_BASE};
18 485 julius
#else
19 505 julius
// No SPI present
20
const int SPI_BASE_ADR[1] = {-1};
21 485 julius
#endif
22 505 julius
#endif
23 485 julius
 
24 505 julius
 
25 393 julius
void
26
spi_core_enable(int core)
27 374 julius
{
28 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPE;
29 374 julius
}
30
 
31 393 julius
void
32
spi_core_disable(int core)
33 374 julius
{
34 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;
35 374 julius
}
36
 
37 393 julius
void
38
spi_core_interrupt_enable(int core)
39 374 julius
{
40 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPIE;
41 374 julius
}
42
 
43 393 julius
void
44
spi_core_interrupt_disable(int core)
45 374 julius
{
46 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;
47 374 julius
}
48
 
49 393 julius
void
50
spi_core_interrupt_flag_clear(int core)
51 374 julius
{
52 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;
53 374 julius
}
54
 
55 393 julius
void
56
spi_core_clock_setup(int core, char polarity, char phase, char rate,
57 374 julius
                          char ext_rate)
58
{
59 505 julius
  char spcr = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR));
60 374 julius
 
61
  if (polarity)
62
    spcr |= SIMPLESPI_SPCR_CPOL;
63
  else
64
    spcr &= ~SIMPLESPI_SPCR_CPOL;
65
 
66
  if (phase)
67
    spcr |= SIMPLESPI_SPCR_CPHA;
68
  else
69
    spcr &= ~SIMPLESPI_SPCR_CPHA;
70
 
71
  spcr = (spcr & ~SIMPLESPI_SPCR_SPR) | (rate & SIMPLESPI_SPCR_SPR);
72
 
73 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) = spcr;
74 374 julius
 
75 505 julius
  char sper = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER));
76 374 julius
 
77
  sper = (sper & ~SIMPLESPI_SPER_ESPR) | (ext_rate & SIMPLESPI_SPER_ESPR);
78
 
79 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER)) = sper;
80 374 julius
 
81
}
82
 
83 393 julius
void
84
spi_core_set_int_count(int core, char cnt)
85 374 julius
{
86 505 julius
  char sper = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER));
87 374 julius
 
88
  sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
89
 
90 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER)) = sper;
91 374 julius
 
92
}
93 415 julius
// No decode on slave select lines, so assert correct bit to select slave
94 393 julius
void
95
spi_core_slave_select(int core, char slave_sel_dec)
96 374 julius
{
97 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
98 374 julius
}
99
 
100 393 julius
int
101
spi_core_data_avail(int core)
102 374 julius
{
103 505 julius
  return !!!(REG8((SPI_BASE_ADR[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);
104 374 julius
}
105
 
106 393 julius
int
107
spi_core_write_avail(int core)
108 374 julius
{
109 505 julius
  return !!!(REG8((SPI_BASE_ADR[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);
110 374 julius
}
111
 
112
// Should call spi_core_write_avail() before calling this, we don't check
113 393 julius
void
114
spi_core_write_data(int core, char data)
115 374 julius
{
116 505 julius
  REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPDR)) = data;
117 374 julius
}
118
 
119 393 julius
char
120
spi_core_read_data(int core)
121 374 julius
{
122 505 julius
  return REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPDR));
123 374 julius
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.