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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 393

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#include "cpu-utils.h"
#include "board.h"
#include "uart.h"
 
const int UART_BASE_ADR[1] = {UART0_BASE};
const int UART_BAUDS[1] = {UART0_BAUD_RATE};
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR(core)                    \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE(core)                     \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR(core)                     \
         do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(int core)
{
        int divisor;
        float float_divisor;
        /* Reset receiver and transmiter */
        REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
        /* Disable all interrupts */
        REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
 
        /* Set 8 bit char, 1 stop bit, no parity */
        REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
        /* Set baud rate */
        float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
        float_divisor += 0.50f; // Ensure round up
        divisor = (int) float_divisor;
 
        REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
        REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
 
        return;
}
 
void uart_putc(int core, char c)
{
        unsigned char lsr;
 
        WAIT_FOR_THRE(core);
        REG8(UART_BASE_ADR[core] + UART_TX) = c;
        if(c == '\n') {
          WAIT_FOR_THRE(core);
          REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
        }
        WAIT_FOR_XMITR(core);
}
 
// Only used when we know THRE is empty, typically in interrupt
void uart_putc_noblock(int core, char c)
{
  REG8(UART_BASE_ADR[core] + UART_TX) = c;
}
 
 
char uart_getc(int core)
{
        unsigned char lsr;
        char c;
 
        WAIT_FOR_CHAR(core);
        c = REG8(UART_BASE_ADR[core] + UART_RX);
        return c;
}
 
int uart_check_for_char(int core)
{
  return CHECK_FOR_CHAR(core);
}
 
void uart_rxint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
}
 
void uart_rxint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
}
 
void uart_txint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
}
 
void uart_txint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
}
 
char uart_get_iir(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_IIR);
}
 
 
char uart_get_lsr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_LSR);
}
 
 
char uart_get_msr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_MSR);
}

Line No.	Rev	Author	Line
1	393	julius	`#include "cpu-utils.h"`
2	349	julius	`#include "board.h"`
3			`#include "uart.h"`
4
5			`const int UART_BASE_ADR[1] = {UART0_BASE};`
6			`const int UART_BAUDS[1] = {UART0_BAUD_RATE};`
7
8			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
9
10			`#define WAIT_FOR_XMITR(core) \`
11			`do { \`
12			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
13			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
14
15			`#define WAIT_FOR_THRE(core) \`
16			`do { \`
17			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
18			`} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)`
19
20			`#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)`
21
22			`#define WAIT_FOR_CHAR(core) \`
23			`do { \`
24			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
25			`} while ((lsr & UART_LSR_DR) != UART_LSR_DR)`
26
27			`#define UART_TX_BUFF_LEN 32`
28			`#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)`
29
30			`char tx_buff[UART_TX_BUFF_LEN];`
31			`volatile int tx_level, rx_level;`
32
33			`void uart_init(int core)`
34			`{`
35			`int divisor;`
36			`float float_divisor;`
37			`/* Reset receiver and transmiter */`
38			`REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT \| UART_FCR_TRIGGER_14;`
39
40			`/* Disable all interrupts */`
41			`REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;`
42
43			`/* Set 8 bit char, 1 stop bit, no parity */`
44			`REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP \| UART_LCR_PARITY);`
45
46			`/* Set baud rate */`
47			`float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);`
48			`float_divisor += 0.50f; // Ensure round up`
49			`divisor = (int) float_divisor;`
50
51			`REG8(UART_BASE_ADR[core] + UART_LCR) \|= UART_LCR_DLAB;`
52			`REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;`
53			`REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;`
54			`REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);`
55
56			`return;`
57			`}`
58
59			`void uart_putc(int core, char c)`
60			`{`
61			`unsigned char lsr;`
62
63			`WAIT_FOR_THRE(core);`
64			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
65			`if(c == '\n') {`
66			`WAIT_FOR_THRE(core);`
67			`REG8(UART_BASE_ADR[core] + UART_TX) = '\r';`
68			`}`
69			`WAIT_FOR_XMITR(core);`
70			`}`
71
72			`// Only used when we know THRE is empty, typically in interrupt`
73			`void uart_putc_noblock(int core, char c)`
74			`{`
75			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
76			`}`
77
78
79			`char uart_getc(int core)`
80			`{`
81			`unsigned char lsr;`
82			`char c;`
83
84			`WAIT_FOR_CHAR(core);`
85			`c = REG8(UART_BASE_ADR[core] + UART_RX);`
86			`return c;`
87			`}`
88
89			`int uart_check_for_char(int core)`
90			`{`
91			`return CHECK_FOR_CHAR(core);`
92			`}`
93
94			`void uart_rxint_enable(int core)`
95			`{`
96			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_RDI;`
97			`}`
98
99			`void uart_rxint_disable(int core)`
100			`{`
101			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);`
102			`}`
103
104			`void uart_txint_enable(int core)`
105			`{`
106			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_THRI;`
107			`}`
108
109			`void uart_txint_disable(int core)`
110			`{`
111			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);`
112			`}`
113
114			`char uart_get_iir(int core)`
115			`{`
116			`return REG8(UART_BASE_ADR[core] + UART_IIR);`
117			`}`
118
119
120			`char uart_get_lsr(int core)`
121			`{`
122			`return REG8(UART_BASE_ADR[core] + UART_LSR);`
123			`}`
124
125
126			`char uart_get_msr(int core)`
127			`{`
128			`return REG8(UART_BASE_ADR[core] + UART_MSR);`
129			`}`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 393