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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 482

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#include "cpu-utils.h"
#include "board.h"
#include "uart.h"
 
const int UART_BASE_ADR[1] = {
#ifdef UART0_BASE
        UART0_BASE
#else
 
#endif
};
const int UART_BAUDS[1] = {
#ifdef UART0_BAUD_RATE
        UART0_BAUD_RATE
#else
 
#endif
};
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR(core)                    \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE(core)                     \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR(core)                     \
         do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(int core)
{
        int divisor;
        float float_divisor;
        /* Reset receiver and transmiter */
        REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
        /* Disable all interrupts */
        REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
 
        /* Set 8 bit char, 1 stop bit, no parity */
        REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
        /* Set baud rate */
        float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
        float_divisor += 0.50f; // Ensure round up
        divisor = (int) float_divisor;
 
        REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
        REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
 
        return;
}
 
void uart_putc(int core, char c)
{
        unsigned char lsr;
 
        WAIT_FOR_THRE(core);
        REG8(UART_BASE_ADR[core] + UART_TX) = c;
        if(c == '\n') {
          WAIT_FOR_THRE(core);
          REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
        }
        WAIT_FOR_XMITR(core);
}
 
// Only used when we know THRE is empty, typically in interrupt
void uart_putc_noblock(int core, char c)
{
  REG8(UART_BASE_ADR[core] + UART_TX) = c;
}
 
 
char uart_getc(int core)
{
        unsigned char lsr;
        char c;
 
        WAIT_FOR_CHAR(core);
        c = REG8(UART_BASE_ADR[core] + UART_RX);
        return c;
}
 
int uart_check_for_char(int core)
{
  return CHECK_FOR_CHAR(core);
}
 
void uart_rxint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
}
 
void uart_rxint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
}
 
void uart_txint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
}
 
void uart_txint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
}
 
char uart_get_iir(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_IIR);
}
 
 
char uart_get_lsr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_LSR);
}
 
 
char uart_get_msr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_MSR);
}

Line No.	Rev	Author	Line
1	393	julius	`#include "cpu-utils.h"`
2	349	julius	`#include "board.h"`
3			`#include "uart.h"`
4
5	482	julius	`const int UART_BASE_ADR[1] = {`
6			`#ifdef UART0_BASE`
7			`UART0_BASE`
8			`#else`
9
10			`#endif`
11			`};`
12			`const int UART_BAUDS[1] = {`
13			`#ifdef UART0_BAUD_RATE`
14			`UART0_BAUD_RATE`
15			`#else`
16
17			`#endif`
18			`};`
19	349	julius
20			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
21
22			`#define WAIT_FOR_XMITR(core) \`
23			`do { \`
24			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
25			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
26
27			`#define WAIT_FOR_THRE(core) \`
28			`do { \`
29			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
30			`} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)`
31
32			`#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)`
33
34			`#define WAIT_FOR_CHAR(core) \`
35			`do { \`
36			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
37			`} while ((lsr & UART_LSR_DR) != UART_LSR_DR)`
38
39			`#define UART_TX_BUFF_LEN 32`
40			`#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)`
41
42			`char tx_buff[UART_TX_BUFF_LEN];`
43			`volatile int tx_level, rx_level;`
44
45			`void uart_init(int core)`
46			`{`
47			`int divisor;`
48			`float float_divisor;`
49			`/* Reset receiver and transmiter */`
50			`REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT \| UART_FCR_TRIGGER_14;`
51
52			`/* Disable all interrupts */`
53			`REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;`
54
55			`/* Set 8 bit char, 1 stop bit, no parity */`
56			`REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP \| UART_LCR_PARITY);`
57
58			`/* Set baud rate */`
59			`float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);`
60			`float_divisor += 0.50f; // Ensure round up`
61			`divisor = (int) float_divisor;`
62
63			`REG8(UART_BASE_ADR[core] + UART_LCR) \|= UART_LCR_DLAB;`
64			`REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;`
65			`REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;`
66			`REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);`
67
68			`return;`
69			`}`
70
71			`void uart_putc(int core, char c)`
72			`{`
73			`unsigned char lsr;`
74
75			`WAIT_FOR_THRE(core);`
76			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
77			`if(c == '\n') {`
78			`WAIT_FOR_THRE(core);`
79			`REG8(UART_BASE_ADR[core] + UART_TX) = '\r';`
80			`}`
81			`WAIT_FOR_XMITR(core);`
82			`}`
83
84			`// Only used when we know THRE is empty, typically in interrupt`
85			`void uart_putc_noblock(int core, char c)`
86			`{`
87			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
88			`}`
89
90
91			`char uart_getc(int core)`
92			`{`
93			`unsigned char lsr;`
94			`char c;`
95
96			`WAIT_FOR_CHAR(core);`
97			`c = REG8(UART_BASE_ADR[core] + UART_RX);`
98			`return c;`
99			`}`
100
101			`int uart_check_for_char(int core)`
102			`{`
103			`return CHECK_FOR_CHAR(core);`
104			`}`
105
106			`void uart_rxint_enable(int core)`
107			`{`
108			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_RDI;`
109			`}`
110
111			`void uart_rxint_disable(int core)`
112			`{`
113			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);`
114			`}`
115
116			`void uart_txint_enable(int core)`
117			`{`
118			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_THRI;`
119			`}`
120
121			`void uart_txint_disable(int core)`
122			`{`
123			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);`
124			`}`
125
126			`char uart_get_iir(int core)`
127			`{`
128			`return REG8(UART_BASE_ADR[core] + UART_IIR);`
129			`}`
130
131
132			`char uart_get_lsr(int core)`
133			`{`
134			`return REG8(UART_BASE_ADR[core] + UART_LSR);`
135			`}`
136
137
138			`char uart_get_msr(int core)`
139			`{`
140			`return REG8(UART_BASE_ADR[core] + UART_MSR);`
141			`}`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 482