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349 |
julius |
/*
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Basic instruction set test
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Requires hardware multiply (uses l.muli and l.mul)
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We specify our own reset and initialisation routines as we don't link
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in the usual initialisation code.
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Based on original or1200 instruction set test
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modified by
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Julius Baxter, julius@opencores.org
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Tadej Markovic, tadej@opencores.org
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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// Check multiply unit is enabled before trying to run this test
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#ifndef OR1200_MULT_IMPLEMENTED
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# error
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# error No multiply unit detected. This test requires hardware multiply support
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# error
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#endif
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* =================================================== [ text ] === */
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.section .text
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/* =================================================== [ start ] === */
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.global _start
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_start:
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julius |
l.jal _cache_init
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349 |
julius |
l.nop
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// Kick off test
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l.jal _main
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l.nop
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/* =================================================== [ main ] === */
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.global _main
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_main:
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l.nop
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l.j _regs
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l.nop
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| 103 |
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_regs:
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l.addi r1,r0,0x1
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l.addi r2,r1,0x2
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l.addi r3,r2,0x4
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l.addi r4,r3,0x8
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l.addi r5,r4,0x10
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l.addi r6,r5,0x20
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l.addi r7,r6,0x40
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l.addi r8,r7,0x80
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l.addi r9,r8,0x100
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l.addi r10,r9,0x200
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l.addi r11,r10,0x400
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l.addi r12,r11,0x800
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l.addi r13,r12,0x1000
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l.addi r14,r13,0x2000
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l.addi r15,r14,0x4000
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l.addi r16,r15,0x8000
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l.sub r31,r0,r1
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l.sub r30,r31,r2
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l.sub r29,r30,r3
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l.sub r28,r29,r4
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l.sub r27,r28,r5
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l.sub r26,r27,r6
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l.sub r25,r26,r7
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l.sub r24,r25,r8
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l.sub r23,r24,r9
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l.sub r22,r23,r10
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l.sub r21,r22,r11
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l.sub r20,r21,r12
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l.sub r19,r20,r13
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l.sub r18,r19,r14
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l.sub r17,r18,r15
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l.sub r16,r17,r16
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l.movhi r31,0x0000
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l.ori r31,r31,0x0040
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l.mtspr r0,r16,0x1234 /* Should be 0xffff0012 */
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l.sw 0(r31),r16
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_mem: l.movhi r3,0x1234
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l.ori r3,r3,0x5678
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l.sw 4(r31),r3
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l.lbz r4,4(r31)
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l.add r8,r8,r4
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l.sb 11(r31),r4
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l.lbz r4,5(r31)
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l.add r8,r8,r4
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l.sb 10(r31),r4
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l.lbz r4,6(r31)
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l.add r8,r8,r4
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l.sb 9(r31),r4
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l.lbz r4,7(r31)
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l.add r8,r8,r4
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l.sb 8(r31),r4
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l.lbs r4,8(r31)
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l.add r8,r8,r4
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l.sb 7(r31),r4
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l.lbs r4,9(r31)
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l.add r8,r8,r4
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l.sb 6(r31),r4
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l.lbs r4,10(r31)
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l.add r8,r8,r4
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l.sb 5(r31),r4
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l.lbs r4,11(r31)
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l.add r8,r8,r4
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l.sb 4(r31),r4
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l.lhz r4,4(r31)
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l.add r8,r8,r4
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l.sh 10(r31),r4
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l.lhz r4,6(r31)
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l.add r8,r8,r4
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l.sh 8(r31),r4
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l.lhs r4,8(r31)
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l.add r8,r8,r4
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l.sh 6(r31),r4
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l.lhs r4,10(r31)
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l.add r8,r8,r4
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| 189 |
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l.sh 4(r31),r4
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| 190 |
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| 191 |
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l.lwz r4,4(r31)
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| 192 |
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l.add r8,r8,r4
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| 193 |
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| 194 |
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l.mtspr r0,r8,0x1234 /* Should be 0x12352af7 */
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| 195 |
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| 196 |
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l.lwz r9,0(r31)
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| 197 |
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l.add r8,r9,r8
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| 198 |
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l.sw 0(r31),r8
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| 199 |
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| 200 |
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| 201 |
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_arith:
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r5,r0,-1
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| 205 |
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l.addi r6,r0,-1
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| 206 |
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l.addi r8,r0,0
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| 207 |
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| 208 |
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l.sub r7,r5,r3
|
| 209 |
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l.sub r8,r3,r5
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| 210 |
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l.add r8,r8,r7
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| 211 |
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| 212 |
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# l.div r7,r7,r4
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| 213 |
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l.add r9,r3,r4
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| 214 |
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l.mul r7,r9,r7
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| 215 |
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# l.divu r7,r7,r4
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| 216 |
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l.add r8,r8,r7
|
| 217 |
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|
| 218 |
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l.mtspr r0,r8,0x1234 /* Should be 0x7ffffffe */
|
| 219 |
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| 220 |
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l.lwz r9,0(r31)
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| 221 |
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l.add r8,r9,r8
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| 222 |
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l.sw 0(r31),r8
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| 223 |
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| 224 |
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| 225 |
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_log:
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| 226 |
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l.addi r3,r0,1
|
| 227 |
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l.addi r4,r0,2
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| 228 |
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l.addi r5,r0,-1
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| 229 |
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l.addi r6,r0,-1
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| 230 |
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l.addi r8,r0,0
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| 231 |
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| 232 |
|
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l.andi r8,r8,1
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| 233 |
|
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l.and r8,r8,r3
|
| 234 |
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| 235 |
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l.xori r8,r5,0xa5a5
|
| 236 |
|
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l.xor r8,r8,r5
|
| 237 |
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| 238 |
|
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l.ori r8,r8,2
|
| 239 |
|
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l.or r8,r8,r4
|
| 240 |
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|
| 241 |
|
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l.mtspr r0,r8,0x1234 /* Should be 0xffffa5a7 */
|
| 242 |
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|
|
| 243 |
|
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l.lwz r9,0(r31)
|
| 244 |
|
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l.add r8,r9,r8
|
| 245 |
|
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l.sw 0(r31),r8
|
| 246 |
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|
| 247 |
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|
| 248 |
|
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_shift:
|
| 249 |
|
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l.addi r3,r0,1
|
| 250 |
|
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l.addi r4,r0,2
|
| 251 |
|
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l.addi r5,r0,-1
|
| 252 |
|
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l.addi r6,r0,-1
|
| 253 |
|
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l.addi r8,r0,0
|
| 254 |
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|
|
| 255 |
|
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l.slli r8,r5,6
|
| 256 |
|
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l.sll r8,r8,r4
|
| 257 |
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|
|
| 258 |
|
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l.srli r8,r8,6
|
| 259 |
|
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l.srl r8,r8,r4
|
| 260 |
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|
|
| 261 |
|
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l.srai r8,r8,2
|
| 262 |
|
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l.sra r8,r8,r4
|
| 263 |
|
|
|
| 264 |
|
|
l.mtspr r0,r8,0x1234 /* Should be 0x000fffff */
|
| 265 |
|
|
|
| 266 |
|
|
l.lwz r9,0(r31)
|
| 267 |
|
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l.add r8,r9,r8
|
| 268 |
|
|
l.sw 0(r31),r8
|
| 269 |
|
|
|
| 270 |
|
|
|
| 271 |
|
|
_flag:
|
| 272 |
|
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l.addi r3,r0,1
|
| 273 |
|
|
l.addi r4,r0,-2
|
| 274 |
|
|
l.addi r8,r0,0
|
| 275 |
|
|
|
| 276 |
|
|
l.sfeq r3,r3
|
| 277 |
|
|
l.mfspr r5,r0,17
|
| 278 |
|
|
l.andi r4,r5,0x200
|
| 279 |
|
|
l.add r8,r8,r4
|
| 280 |
|
|
|
| 281 |
|
|
l.sfeq r3,r4
|
| 282 |
|
|
l.mfspr r5,r0,17
|
| 283 |
|
|
l.andi r4,r5,0x200
|
| 284 |
|
|
l.add r8,r8,r4
|
| 285 |
|
|
|
| 286 |
|
|
l.sfeqi r3,1
|
| 287 |
|
|
l.mfspr r5,r0,17
|
| 288 |
|
|
l.andi r4,r5,0x200
|
| 289 |
|
|
l.add r8,r8,r4
|
| 290 |
|
|
|
| 291 |
|
|
l.sfeqi r3,-2
|
| 292 |
|
|
l.mfspr r5,r0,17
|
| 293 |
|
|
l.andi r4,r5,0x200
|
| 294 |
|
|
l.add r8,r8,r4
|
| 295 |
|
|
|
| 296 |
|
|
l.sfne r3,r3
|
| 297 |
|
|
l.mfspr r5,r0,17
|
| 298 |
|
|
l.andi r4,r5,0x200
|
| 299 |
|
|
l.add r8,r8,r4
|
| 300 |
|
|
|
| 301 |
|
|
l.sfne r3,r4
|
| 302 |
|
|
l.mfspr r5,r0,17
|
| 303 |
|
|
l.andi r4,r5,0x200
|
| 304 |
|
|
l.add r8,r8,r4
|
| 305 |
|
|
|
| 306 |
|
|
l.sfnei r3,1
|
| 307 |
|
|
l.mfspr r5,r0,17
|
| 308 |
|
|
l.andi r4,r5,0x200
|
| 309 |
|
|
l.add r8,r8,r4
|
| 310 |
|
|
|
| 311 |
|
|
l.sfnei r3,-2
|
| 312 |
|
|
l.mfspr r5,r0,17
|
| 313 |
|
|
l.andi r4,r5,0x200
|
| 314 |
|
|
l.add r8,r8,r4
|
| 315 |
|
|
|
| 316 |
|
|
l.sfgtu r3,r3
|
| 317 |
|
|
l.mfspr r5,r0,17
|
| 318 |
|
|
l.andi r4,r5,0x200
|
| 319 |
|
|
l.add r8,r8,r4
|
| 320 |
|
|
|
| 321 |
|
|
l.sfgtu r3,r4
|
| 322 |
|
|
l.mfspr r5,r0,17
|
| 323 |
|
|
l.andi r4,r5,0x200
|
| 324 |
|
|
l.add r8,r8,r4
|
| 325 |
|
|
|
| 326 |
|
|
l.sfgtui r3,1
|
| 327 |
|
|
l.mfspr r5,r0,17
|
| 328 |
|
|
l.andi r4,r5,0x200
|
| 329 |
|
|
l.add r8,r8,r4
|
| 330 |
|
|
|
| 331 |
|
|
l.sfgtui r3,-2
|
| 332 |
|
|
l.mfspr r5,r0,17
|
| 333 |
|
|
l.andi r4,r5,0x200
|
| 334 |
|
|
l.add r8,r8,r4
|
| 335 |
|
|
|
| 336 |
|
|
l.sfgeu r3,r3
|
| 337 |
|
|
l.mfspr r5,r0,17
|
| 338 |
|
|
l.andi r4,r5,0x200
|
| 339 |
|
|
l.add r8,r8,r4
|
| 340 |
|
|
|
| 341 |
|
|
l.sfgeu r3,r4
|
| 342 |
|
|
l.mfspr r5,r0,17
|
| 343 |
|
|
l.andi r4,r5,0x200
|
| 344 |
|
|
l.add r8,r8,r4
|
| 345 |
|
|
|
| 346 |
|
|
l.sfgeui r3,1
|
| 347 |
|
|
l.mfspr r5,r0,17
|
| 348 |
|
|
l.andi r4,r5,0x200
|
| 349 |
|
|
l.add r8,r8,r4
|
| 350 |
|
|
|
| 351 |
|
|
l.sfgeui r3,-2
|
| 352 |
|
|
l.mfspr r5,r0,17
|
| 353 |
|
|
l.andi r4,r5,0x200
|
| 354 |
|
|
l.add r8,r8,r4
|
| 355 |
|
|
|
| 356 |
|
|
l.sfltu r3,r3
|
| 357 |
|
|
l.mfspr r5,r0,17
|
| 358 |
|
|
l.andi r4,r5,0x200
|
| 359 |
|
|
l.add r8,r8,r4
|
| 360 |
|
|
|
| 361 |
|
|
l.sfltu r3,r4
|
| 362 |
|
|
l.mfspr r5,r0,17
|
| 363 |
|
|
l.andi r4,r5,0x200
|
| 364 |
|
|
l.add r8,r8,r4
|
| 365 |
|
|
|
| 366 |
|
|
l.sfltui r3,1
|
| 367 |
|
|
l.mfspr r5,r0,17
|
| 368 |
|
|
l.andi r4,r5,0x200
|
| 369 |
|
|
l.add r8,r8,r4
|
| 370 |
|
|
|
| 371 |
|
|
l.sfltui r3,-2
|
| 372 |
|
|
l.mfspr r5,r0,17
|
| 373 |
|
|
l.andi r4,r5,0x200
|
| 374 |
|
|
l.add r8,r8,r4
|
| 375 |
|
|
|
| 376 |
|
|
l.sfleu r3,r3
|
| 377 |
|
|
l.mfspr r5,r0,17
|
| 378 |
|
|
l.andi r4,r5,0x200
|
| 379 |
|
|
l.add r8,r8,r4
|
| 380 |
|
|
|
| 381 |
|
|
l.sfleu r3,r4
|
| 382 |
|
|
l.mfspr r5,r0,17
|
| 383 |
|
|
l.andi r4,r5,0x200
|
| 384 |
|
|
l.add r8,r8,r4
|
| 385 |
|
|
|
| 386 |
|
|
l.sfleui r3,1
|
| 387 |
|
|
l.mfspr r5,r0,17
|
| 388 |
|
|
l.andi r4,r5,0x200
|
| 389 |
|
|
l.add r8,r8,r4
|
| 390 |
|
|
|
| 391 |
|
|
l.sfleui r3,-2
|
| 392 |
|
|
l.mfspr r5,r0,17
|
| 393 |
|
|
l.andi r4,r5,0x200
|
| 394 |
|
|
l.add r8,r8,r4
|
| 395 |
|
|
|
| 396 |
|
|
l.sfgts r3,r3
|
| 397 |
|
|
l.mfspr r5,r0,17
|
| 398 |
|
|
l.andi r4,r5,0x200
|
| 399 |
|
|
l.add r8,r8,r4
|
| 400 |
|
|
|
| 401 |
|
|
l.sfgts r3,r4
|
| 402 |
|
|
l.mfspr r5,r0,17
|
| 403 |
|
|
l.andi r4,r5,0x200
|
| 404 |
|
|
l.add r8,r8,r4
|
| 405 |
|
|
|
| 406 |
|
|
l.sfgtsi r3,1
|
| 407 |
|
|
l.mfspr r5,r0,17
|
| 408 |
|
|
l.andi r4,r5,0x200
|
| 409 |
|
|
l.add r8,r8,r4
|
| 410 |
|
|
|
| 411 |
|
|
l.sfgtsi r3,-2
|
| 412 |
|
|
l.mfspr r5,r0,17
|
| 413 |
|
|
l.andi r4,r5,0x200
|
| 414 |
|
|
l.add r8,r8,r4
|
| 415 |
|
|
|
| 416 |
|
|
l.sfges r3,r3
|
| 417 |
|
|
l.mfspr r5,r0,17
|
| 418 |
|
|
l.andi r4,r5,0x200
|
| 419 |
|
|
l.add r8,r8,r4
|
| 420 |
|
|
|
| 421 |
|
|
l.sfges r3,r4
|
| 422 |
|
|
l.mfspr r5,r0,17
|
| 423 |
|
|
l.andi r4,r5,0x200
|
| 424 |
|
|
l.add r8,r8,r4
|
| 425 |
|
|
|
| 426 |
|
|
l.sfgesi r3,1
|
| 427 |
|
|
l.mfspr r5,r0,17
|
| 428 |
|
|
l.andi r4,r5,0x200
|
| 429 |
|
|
l.add r8,r8,r4
|
| 430 |
|
|
|
| 431 |
|
|
l.sfgesi r3,-2
|
| 432 |
|
|
l.mfspr r5,r0,17
|
| 433 |
|
|
l.andi r4,r5,0x200
|
| 434 |
|
|
l.add r8,r8,r4
|
| 435 |
|
|
|
| 436 |
|
|
l.sflts r3,r3
|
| 437 |
|
|
l.mfspr r5,r0,17
|
| 438 |
|
|
l.andi r4,r5,0x200
|
| 439 |
|
|
l.add r8,r8,r4
|
| 440 |
|
|
|
| 441 |
|
|
l.sflts r3,r4
|
| 442 |
|
|
l.mfspr r5,r0,17
|
| 443 |
|
|
l.andi r4,r5,0x200
|
| 444 |
|
|
l.add r8,r8,r4
|
| 445 |
|
|
|
| 446 |
|
|
l.sfltsi r3,1
|
| 447 |
|
|
l.mfspr r5,r0,17
|
| 448 |
|
|
l.andi r4,r5,0x200
|
| 449 |
|
|
l.add r8,r8,r4
|
| 450 |
|
|
|
| 451 |
|
|
l.sfltsi r3,-2
|
| 452 |
|
|
l.mfspr r5,r0,17
|
| 453 |
|
|
l.andi r4,r5,0x200
|
| 454 |
|
|
l.add r8,r8,r4
|
| 455 |
|
|
|
| 456 |
|
|
l.sfles r3,r3
|
| 457 |
|
|
l.mfspr r5,r0,17
|
| 458 |
|
|
l.andi r4,r5,0x200
|
| 459 |
|
|
l.add r8,r8,r4
|
| 460 |
|
|
|
| 461 |
|
|
l.sfles r3,r4
|
| 462 |
|
|
l.mfspr r5,r0,17
|
| 463 |
|
|
l.andi r4,r5,0x200
|
| 464 |
|
|
l.add r8,r8,r4
|
| 465 |
|
|
|
| 466 |
|
|
l.sflesi r3,1
|
| 467 |
|
|
l.mfspr r5,r0,17
|
| 468 |
|
|
l.andi r4,r5,0x200
|
| 469 |
|
|
l.add r8,r8,r4
|
| 470 |
|
|
|
| 471 |
|
|
l.sflesi r3,-2
|
| 472 |
|
|
l.mfspr r5,r0,17
|
| 473 |
|
|
l.andi r4,r5,0x200
|
| 474 |
|
|
l.add r8,r8,r4
|
| 475 |
|
|
|
| 476 |
|
|
l.mtspr r0,r8,0x1234 /* Should be 0x00002800 */
|
| 477 |
|
|
|
| 478 |
|
|
l.lwz r9,0(r31)
|
| 479 |
|
|
l.add r8,r9,r8
|
| 480 |
|
|
l.sw 0(r31),r8
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
_dslot:
|
| 484 |
|
|
l.addi r14,r0,0x4 /* inc. loop cnt. - must be non-zero */
|
| 485 |
|
|
/* and operand at 1st operation */
|
| 486 |
|
|
l.addi r15,r0,0x14 /* inc. cnt. limit value (4+4+4+4+4) */
|
| 487 |
|
|
l.addi r21,r0,0x40 /* mul. by 2 cnt. limit value (4*2*2*2*2) */
|
| 488 |
|
|
l.addi r16,r0,0x10 /* dec. loop cnt. - limits at 0 */
|
| 489 |
|
|
/* loop counters are changed by 4 due */
|
| 490 |
|
|
/* to value is used by l.lwz/l.sw */
|
| 491 |
|
|
l.addi r17,r0,7 /* operand at 2nd operation */
|
| 492 |
|
|
/* and test result */
|
| 493 |
|
|
l.addi r18,r0,8 /* operand at 2nd operation */
|
| 494 |
|
|
l.addi r19,r0,9 /* operand at 3rd operation */
|
| 495 |
|
|
l.addi r20,r0,-1 /* xor every intermediate result by */
|
| 496 |
|
|
/* value 0xffffffff */
|
| 497 |
|
|
|
| 498 |
|
|
l.sw (0x0)(r14),r0 /* init RAM to zero */
|
| 499 |
|
|
l.sw (0x4)(r14),r0
|
| 500 |
|
|
l.sw (0x8)(r14),r0
|
| 501 |
|
|
l.sw (0xc)(r14),r0
|
| 502 |
|
|
l.sw (0x10)(r14),r0
|
| 503 |
|
|
l.sw (0x14)(r14),r0
|
| 504 |
|
|
l.sw (0x18)(r14),r0
|
| 505 |
|
|
l.sw (0x1c)(r14),r0
|
| 506 |
|
|
l.sw (0x20)(r14),r0
|
| 507 |
|
|
l.sw (0x24)(r14),r0
|
| 508 |
|
|
l.sw (0x28)(r14),r0
|
| 509 |
|
|
l.sw (0x2c)(r14),r0
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
/* ins. in dslot - loop 1: */
|
| 513 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 514 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 515 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 516 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 517 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 518 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 519 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 520 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 521 |
|
|
_D1:
|
| 522 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 523 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 524 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 525 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 526 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 527 |
|
|
l.sfeqi r16,0
|
| 528 |
|
|
l.bf _D2s
|
| 529 |
|
|
l.add r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 530 |
|
|
l.j _D1
|
| 531 |
|
|
l.addi r19,r19,1 /* r19..3rd operation operand */
|
| 532 |
|
|
|
| 533 |
|
|
|
| 534 |
|
|
/* ins. in dslot - loop 2: */
|
| 535 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 536 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 537 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 538 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 539 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 540 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 541 |
|
|
_D2s:
|
| 542 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 543 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 544 |
|
|
_D2:
|
| 545 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 546 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 547 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 548 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 549 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 550 |
|
|
l.sfgeu r14,r15
|
| 551 |
|
|
l.bf _D3s
|
| 552 |
|
|
l.add r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 553 |
|
|
l.j _D2
|
| 554 |
|
|
l.addi r19,r17,1 /* r19,r17..3rd operation operand */
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
/* ins. in dslot - loop 3: */
|
| 558 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 559 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 560 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 561 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 562 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 563 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 564 |
|
|
_D3s:
|
| 565 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 566 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 567 |
|
|
_D3:
|
| 568 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 569 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 570 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 571 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 572 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 573 |
|
|
l.sfeqi r16,0
|
| 574 |
|
|
l.bf _D4s
|
| 575 |
|
|
l.add r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 576 |
|
|
l.j _D3
|
| 577 |
|
|
l.muli r19,r19,2 /* r19..3rd operation operand */
|
| 578 |
|
|
|
| 579 |
|
|
|
| 580 |
|
|
/* ins. in dslot - loop 4: */
|
| 581 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 582 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 583 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 584 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 585 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 586 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 587 |
|
|
_D4s:
|
| 588 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 589 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 590 |
|
|
_D4:
|
| 591 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 592 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 593 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 594 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 595 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 596 |
|
|
l.sfgeu r14,r15
|
| 597 |
|
|
l.bf _D5s
|
| 598 |
|
|
l.add r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 599 |
|
|
l.j _D4
|
| 600 |
|
|
l.muli r19,r17,1 /* r19,r17..3rd operation operand */
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
/* ins. in dslot - loop 5: */
|
| 604 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 605 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 606 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 607 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 608 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 609 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 610 |
|
|
_D5s:
|
| 611 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 612 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 613 |
|
|
_D5:
|
| 614 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 615 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 616 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 617 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 618 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 619 |
|
|
l.sfeqi r16,0
|
| 620 |
|
|
l.bf _D6s
|
| 621 |
|
|
l.mul r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 622 |
|
|
l.j _D5
|
| 623 |
|
|
l.addi r19,r19,1 /* r19..3rd operation operand */
|
| 624 |
|
|
|
| 625 |
|
|
|
| 626 |
|
|
/* ins. in dslot - loop 6: */
|
| 627 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 628 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 629 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 630 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 631 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 632 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 633 |
|
|
_D6s:
|
| 634 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 635 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 636 |
|
|
_D6:
|
| 637 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 638 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 639 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 640 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 641 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 642 |
|
|
l.sfgeu r14,r15
|
| 643 |
|
|
l.bf _D7s
|
| 644 |
|
|
l.mul r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 645 |
|
|
l.j _D6
|
| 646 |
|
|
l.addi r19,r17,1 /* r19,r17..3rd operation operand */
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
/* ins. in dslot - loop 7: */
|
| 650 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 651 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 652 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 653 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 654 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 655 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 656 |
|
|
_D7s:
|
| 657 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 658 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 659 |
|
|
_D7:
|
| 660 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 661 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 662 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 663 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 664 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 665 |
|
|
l.sfeqi r16,0
|
| 666 |
|
|
l.bf _D8s
|
| 667 |
|
|
l.mul r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 668 |
|
|
l.j _D7
|
| 669 |
|
|
l.muli r19,r19,2 /* r19..3rd operation operand */
|
| 670 |
|
|
|
| 671 |
|
|
|
| 672 |
|
|
/* ins. in dslot - loop 8: */
|
| 673 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 674 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 675 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 676 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 677 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 678 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 679 |
|
|
_D8s:
|
| 680 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 681 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 682 |
|
|
_D8:
|
| 683 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 684 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 685 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 686 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 687 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 688 |
|
|
l.sfgeu r14,r15
|
| 689 |
|
|
l.bf _D9s
|
| 690 |
|
|
l.mul r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 691 |
|
|
l.j _D8
|
| 692 |
|
|
l.muli r19,r17,1 /* r19,r17..3rd operation operand */
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
/* ins. in dslot - loop 9: */
|
| 696 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 697 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 698 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 699 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 700 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 701 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 702 |
|
|
_D9s:
|
| 703 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 704 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 705 |
|
|
_D9:
|
| 706 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 707 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 708 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 709 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 710 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 711 |
|
|
l.sfeqi r16,0
|
| 712 |
|
|
l.bf _D10s
|
| 713 |
|
|
l.add r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 714 |
|
|
l.j _D9
|
| 715 |
|
|
l.addi r19,r19,1 /* r19..3rd operation operand */
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
/* ins. in dslot - loop 10: */
|
| 719 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 720 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 721 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 722 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 723 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 724 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 725 |
|
|
_D10s:
|
| 726 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 727 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 728 |
|
|
_D10:
|
| 729 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 730 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 731 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 732 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 733 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 734 |
|
|
l.sfgeu r14,r21
|
| 735 |
|
|
l.bf _D11s
|
| 736 |
|
|
l.add r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 737 |
|
|
l.j _D10
|
| 738 |
|
|
l.addi r19,r17,1 /* r19,r17..3rd operation operand */
|
| 739 |
|
|
|
| 740 |
|
|
|
| 741 |
|
|
/* ins. in dslot - loop 11: */
|
| 742 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 743 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 744 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 745 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 746 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 747 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 748 |
|
|
_D11s:
|
| 749 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 750 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 751 |
|
|
_D11:
|
| 752 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 753 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 754 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 755 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 756 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 757 |
|
|
l.sfeqi r16,0
|
| 758 |
|
|
l.bf _D12s
|
| 759 |
|
|
l.add r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 760 |
|
|
l.j _D11
|
| 761 |
|
|
l.muli r19,r19,2 /* r19..3rd operation operand */
|
| 762 |
|
|
|
| 763 |
|
|
|
| 764 |
|
|
/* ins. in dslot - loop 12: */
|
| 765 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 766 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 767 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 768 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 769 |
|
|
/* 2nd operation after branch/before jump is SINGLE cycle */
|
| 770 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 771 |
|
|
_D12s:
|
| 772 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 773 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 774 |
|
|
_D12:
|
| 775 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 776 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 777 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 778 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 779 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 780 |
|
|
l.sfgeu r14,r21
|
| 781 |
|
|
l.bf _D13s
|
| 782 |
|
|
l.add r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 783 |
|
|
l.j _D12
|
| 784 |
|
|
l.muli r19,r17,1 /* r19,r17..3rd operation operand */
|
| 785 |
|
|
|
| 786 |
|
|
|
| 787 |
|
|
/* ins. in dslot - loop 13: */
|
| 788 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 789 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 790 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 791 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 792 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 793 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 794 |
|
|
_D13s:
|
| 795 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 796 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 797 |
|
|
_D13:
|
| 798 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 799 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 800 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 801 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 802 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 803 |
|
|
l.sfeqi r16,0
|
| 804 |
|
|
l.bf _D14s
|
| 805 |
|
|
l.mul r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 806 |
|
|
l.j _D13
|
| 807 |
|
|
l.addi r19,r19,1 /* r19..3rd operation operand */
|
| 808 |
|
|
|
| 809 |
|
|
|
| 810 |
|
|
/* ins. in dslot - loop 14: */
|
| 811 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 812 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 813 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 814 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 815 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 816 |
|
|
/* 3rd operation after jump is SINGLE cycle */
|
| 817 |
|
|
_D14s:
|
| 818 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 819 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 820 |
|
|
_D14:
|
| 821 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 822 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 823 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 824 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 825 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 826 |
|
|
l.sfgeu r14,r21
|
| 827 |
|
|
l.bf _D15s
|
| 828 |
|
|
l.mul r17,r17,r18 /* r17,r18..2nd opertion operands */
|
| 829 |
|
|
l.j _D14
|
| 830 |
|
|
l.addi r19,r17,1 /* r19,r17..3rd operation operand */
|
| 831 |
|
|
|
| 832 |
|
|
|
| 833 |
|
|
/* ins. in dslot - loop 15: */
|
| 834 |
|
|
/* 1st operation operand before branch is NOT used to set flag */
|
| 835 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 836 |
|
|
/* 2nd and 3rd operation operands before and after jump are NOT related */
|
| 837 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 838 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 839 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 840 |
|
|
_D15s:
|
| 841 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 842 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 843 |
|
|
_D15:
|
| 844 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 845 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 846 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 847 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 848 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 849 |
|
|
l.sfeqi r16,0
|
| 850 |
|
|
l.bf _D16s
|
| 851 |
|
|
l.mul r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 852 |
|
|
l.j _D15
|
| 853 |
|
|
l.muli r19,r19,2 /* r19..3rd operation operand */
|
| 854 |
|
|
|
| 855 |
|
|
|
| 856 |
|
|
/* ins. in dslot - loop 16: */
|
| 857 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 858 |
|
|
/* 1st and 2nd operation operands before and after branch are related */
|
| 859 |
|
|
/* 2nd and 3rd operation operands before and after jump are related */
|
| 860 |
|
|
/* 1st operation before branch is MULTI cycle */
|
| 861 |
|
|
/* 2nd operation after branch/before jump is MULTI cycle */
|
| 862 |
|
|
/* 3rd operation after jump is MULTI cycle */
|
| 863 |
|
|
_D16s:
|
| 864 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 865 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 866 |
|
|
_D16:
|
| 867 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 868 |
|
|
l.add r17,r17,r19 /* merge test case operands */
|
| 869 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 870 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 871 |
|
|
l.muli r14,r14,2 /* mul. cnt. - r14..1st operation operand */
|
| 872 |
|
|
l.sfgeu r14,r21
|
| 873 |
|
|
l.bf _D17s
|
| 874 |
|
|
l.mul r17,r17,r14 /* r17,r14..2nd opertion operands */
|
| 875 |
|
|
l.j _D16
|
| 876 |
|
|
l.muli r19,r17,1 /* r19,r17..3rd operation operand */
|
| 877 |
|
|
|
| 878 |
|
|
|
| 879 |
|
|
/* ins. in dslot - loop 17: */
|
| 880 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 881 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 882 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 883 |
|
|
/* 2nd operation after branch/before jump is SW */
|
| 884 |
|
|
_D17s:
|
| 885 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 886 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 887 |
|
|
_D17:
|
| 888 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 889 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 890 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 891 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 892 |
|
|
l.sfgeu r14,r15
|
| 893 |
|
|
l.bnf _D17
|
| 894 |
|
|
l.sw 0(r16),r17 /* r16,r17..2nd opertion operands */
|
| 895 |
|
|
|
| 896 |
|
|
|
| 897 |
|
|
/* ins. in dslot - loop 18: */
|
| 898 |
|
|
/* 1st operation operand before branch is used to set flag */
|
| 899 |
|
|
/* 1st and 2nd operation operands before and after branch are NOT related */
|
| 900 |
|
|
/* 1st operation before branch is SINGLE cycle */
|
| 901 |
|
|
/* 2nd operation after branch/before jump is LWZ */
|
| 902 |
|
|
l.addi r14,r0,0x4 /* init inc. loop cnt. */
|
| 903 |
|
|
l.addi r16,r0,0x10 /* init dec. loop cnt. */
|
| 904 |
|
|
_D18:
|
| 905 |
|
|
l.add r17,r17,r22 /* merge test case operands */
|
| 906 |
|
|
l.add r17,r17,r14 /* merge test case operands */
|
| 907 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 908 |
|
|
l.addi r16,r16,-4 /* dec. cnt. */
|
| 909 |
|
|
l.addi r14,r14,4 /* inc. cnt. - r14..1st operation operand */
|
| 910 |
|
|
l.sfgeu r14,r15
|
| 911 |
|
|
l.bnf _D18
|
| 912 |
|
|
l.lwz r22,0(r16) /* r16,r22..2nd opertion operands */
|
| 913 |
|
|
|
| 914 |
|
|
|
| 915 |
|
|
/* following are ins. in dslot in three different JUMPs: l.jal, l.jr, l.j */
|
| 916 |
|
|
l.add r17,r17,r22 /* merge test case operands */
|
| 917 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 918 |
|
|
l.jal _D19
|
| 919 |
|
|
l.muli r17,r17,2
|
| 920 |
|
|
l.add r17,r17,r18
|
| 921 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 922 |
|
|
l.j _D20
|
| 923 |
|
|
l.sub r18,r18,r17
|
| 924 |
|
|
|
| 925 |
|
|
_D19:
|
| 926 |
|
|
l.addi r17,r17,1
|
| 927 |
|
|
l.xor r17,r17,r20 /* invert test result value */
|
| 928 |
|
|
l.jr r9
|
| 929 |
|
|
l.addi r18,r18,8
|
| 930 |
|
|
|
| 931 |
|
|
_D20:
|
| 932 |
|
|
l.mul r17,r17,r18 /* r17 shold be 0xb093a787 */
|
| 933 |
|
|
l.movhi r18,hi(0xb093a787)
|
| 934 |
|
|
l.ori r18,r18,lo(0xb093a787)
|
| 935 |
|
|
l.sub r17,r17,r18 /* r17 used further in code */
|
| 936 |
|
|
l.nop
|
| 937 |
|
|
l.nop
|
| 938 |
|
|
|
| 939 |
|
|
|
| 940 |
|
|
_jump:
|
| 941 |
|
|
l.add r8,r0,r17
|
| 942 |
|
|
|
| 943 |
|
|
l.j _T1
|
| 944 |
|
|
l.addi r8,r8,1
|
| 945 |
|
|
|
| 946 |
|
|
_T2: l.or r10,r0,r9
|
| 947 |
|
|
l.jalr r10
|
| 948 |
|
|
l.addi r8,r8,1
|
| 949 |
|
|
|
| 950 |
|
|
_T1: l.jal _T2
|
| 951 |
|
|
l.addi r8,r8,1
|
| 952 |
|
|
|
| 953 |
|
|
l.sfeqi r0,0
|
| 954 |
|
|
l.bf _T3
|
| 955 |
|
|
l.addi r8,r8,1
|
| 956 |
|
|
|
| 957 |
|
|
_T3: l.sfeqi r0,1
|
| 958 |
|
|
l.bf _T4
|
| 959 |
|
|
l.addi r8,r8,1
|
| 960 |
|
|
|
| 961 |
|
|
l.addi r8,r8,1
|
| 962 |
|
|
|
| 963 |
|
|
_T4: l.sfeqi r0,0
|
| 964 |
|
|
l.bnf _T5
|
| 965 |
|
|
l.addi r8,r8,1
|
| 966 |
|
|
|
| 967 |
|
|
l.addi r8,r8,1
|
| 968 |
|
|
|
| 969 |
|
|
_T5: l.sfeqi r0,1
|
| 970 |
|
|
l.bnf _T6
|
| 971 |
|
|
l.addi r8,r8,1
|
| 972 |
|
|
|
| 973 |
|
|
l.addi r8,r8,1
|
| 974 |
|
|
|
| 975 |
|
|
_T6: l.movhi r3,hi(_T7)
|
| 976 |
|
|
l.ori r3,r3,lo(_T7)
|
| 977 |
|
|
l.mtspr r0,r3,32
|
| 978 |
|
|
l.mfspr r5,r0,17
|
| 979 |
|
|
l.mtspr r0,r5,64
|
| 980 |
|
|
l.rfe
|
| 981 |
|
|
l.addi r8,r8,1
|
| 982 |
|
|
|
| 983 |
|
|
l.addi r8,r8,1
|
| 984 |
|
|
|
| 985 |
|
|
_T7: l.mtspr r0,r8,0x1234 /* Should be 0x00000000a */
|
| 986 |
|
|
|
| 987 |
|
|
l.lwz r9,0(r31)
|
| 988 |
|
|
l.add r8,r9,r8
|
| 989 |
|
|
l.sw 0(r31),r8
|
| 990 |
|
|
|
| 991 |
|
|
l.lwz r9,0(r31)
|
| 992 |
|
|
l.movhi r3,0xcc69
|
| 993 |
|
|
l.ori r3,r3,0xe5fb
|
| 994 |
|
|
l.add r3,r8,r3 /* Should be 0xdeaddead */
|
| 995 |
|
|
|
| 996 |
|
|
l.movhi r4, 0x5ead
|
| 997 |
425 |
julius |
l.ori r4, r4, 0xdea0
|
| 998 |
|
|
l.sub r3, r3, r4 /* Should now be 0x8000000d */
|
| 999 |
|
|
l.nop 0x2
|
| 1000 |
|
|
l.ori r3, r0, 0 /* Clear R3 */
|
| 1001 |
|
|
l.nop 0x1 /* Exit simulation */
|
| 1002 |
530 |
julius |
l.nop
|
| 1003 |
|
|
l.nop
|
