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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-cy.S] - Blame information for rev 714

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1 502 julius 
/*
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        OR1200 carry bit checking
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        Carry generated on all adds which we interpret to be
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        unsigned. The CPU will generate both CY and OV.
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        CY is generated when unsigned values generate an extra bit.
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        OV is when the values, interpreted as signed, cannot have
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        the result displayed as it is too large.
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        OV is not checked here. Just CY generation and inclusion by
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        the l.addc and l.addic instructions.
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13 
        Very basic, testing.
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TODO:    Substraction carry out testing.
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17 
        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
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*/
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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/* =================================================== [ exceptions ] === */
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        .section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        /* Clear status register */
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        l.ori r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Jump to program initialisation code */
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        .global _start
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        l.movhi r4, hi(_start)
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        l.ori r4, r4, lo(_start)
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        l.jr    r4
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        l.nop
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        .org 0x600
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        l.nop 0x1
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/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
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        .org 0x700
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#ifndef OR1200_IMPL_ADDC
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        // No problem - instruction not supported
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        l.movhi r3, hi(0x8000000d)
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        l.ori   r3, r3, lo(0x8000000d)
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        l.nop   0x2
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        l.ori   r3, r0, 0
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#else
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        l.ori   r3, r0, 1
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#endif
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        l.nop   0x1
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/* ---[ 0xb00: Range exception ]---------------------------------------- */
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        .org 0xb00
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        l.sw    0(r0), r3
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        l.ori   r3, r0, 0xaaee
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        l.nop   0x2
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        l.lwz   r3, 0(r0)
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        l.rfe
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/* =================================================== [ text ] === */
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        .section .text
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/* =================================================== [ start ] === */
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        .global _start
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_start:
105 530 julius 
        // Clear regs
106 502 julius 
        l.movhi r1, 0
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        l.movhi r2, 0
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        l.movhi r3, 0
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        l.movhi r4, 0
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        l.movhi r5, 0
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        l.movhi r6, 0
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#ifdef OR1200_IMPL_CY
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        // Kick off test
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        l.jal   _main
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#else
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        // Not supported, exit test
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        l.j     _finish
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#endif
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        l.nop
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/* =================================================== [ main ] === */
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#define CHECK_CY_CLEAR                  \
127 530 julius 
        l.mfspr r6, r0, SPR_SR  ;       \
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        l.andi  r6, r6, SPR_SR_CY ;     \
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        l.sfne  r6, r0            ;     \
130 502 julius 
        l.bf    _fail             ;     \
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        l.nop
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#define CHECK_CY_SET                    \
134 530 julius 
        l.mfspr r6, r0, SPR_SR  ;       \
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        l.andi  r6, r6, SPR_SR_CY ;     \
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        l.sfnei r6, SPR_SR_CY     ;     \
137 502 julius 
        l.bf    _fail             ;     \
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        l.nop
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        .global _main
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_main:
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        // Set up some values, check the CY bit is cleared from reset
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        CHECK_CY_CLEAR
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        // A large unsigned value
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        l.movhi r4, 0xffff
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        l.ori   r4, r4, 0xefff
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        // A value large enough to cause carry
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        l.ori   r5, r0, 0x1001
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        l.add   r3, r5, r4      ;// Should set CY
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        l.nop   0x2
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        CHECK_CY_SET
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        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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        l.addi  r3, r4, 0x1001  ;// Should set CY
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        l.nop   0x2
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        CHECK_CY_SET
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        l.addi  r3, r4, 0x1000  ;// Shouldn't set CY
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        l.nop   0x2
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        CHECK_CY_CLEAR
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        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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        // Check use of carry - l.addc
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        l.addi  r3, r4, 0x1001  ;// Should set CY
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        ;; // Consequtive instructions
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        l.addc  r3, r3, r5      ;// r3 should be 0x1002
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        l.nop   0x2             ;// Report
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        l.sfnei r3, 0x1002
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        l.bf    _fail
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        l.nop
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        l.add   r3, r4, r5      ;// Should set CY
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        l.nop                   ;// 1 delay instruction
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        l.addc  r3, r3, r5      ;// r3 should be 0x1002
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        l.nop   0x2             ;// Report
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        l.sfnei r3, 0x1002
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        l.bf    _fail
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        l.nop
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        l.add   r3, r4, r5      ;// Should set
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        l.nop   0x2             ;// 1 delay instruction
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        l.nop                   ;// 2nd delay instruction
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        l.addc  r3, r3, r5      ;// r3 should be 0x1002
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        l.nop   0x2             ;// Report
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        l.sfnei r3, 0x1002
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        l.bf    _fail
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        l.nop
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        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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        // Check use of carry - l.addic
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        l.addi  r3, r4, 0x1001  ;// Should set CY
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        ;; // Consequtive instructions
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        l.addic r3, r3, 0x1     ;// r3 should be 2
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        l.nop   0x2             ;// Report
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209 
        l.sfnei r3, 0x2
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        l.bf    _fail
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        l.nop
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213 
        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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216 
        l.add   r3, r4, r5      ;// Should set CY
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        l.nop                   ;// 1 delay instruction
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        l.addic r3, r3, 0x1     ;// r3 should be 2
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        l.nop   0x2             ;// Report
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221 
        l.sfnei r3, 0x2
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        l.bf    _fail
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        l.nop
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        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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228 
        l.add   r3, r4, r5      ;// Should set
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        l.nop   0x2             ;// 1 delay instruction
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        l.nop                   ;// 2nd delay instruction
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        l.addic r3, r3, 0x1     ;// r3 should be 2
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        l.nop   0x2             ;// Report
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234 
        l.sfnei r3, 0x2
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        l.bf    _fail
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        l.nop
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238 
        l.add   r3, r0, r0      ;// Should clear CY
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        CHECK_CY_CLEAR
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241 
        // Add with carry and generate carry with l.addc
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243 
        l.add   r3, r4, r5
244 
        l.addc  r3, r4, r5
245 
        l.nop   0x2
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247 
        l.sfnei r3, 0x1
248 
        l.bf    _fail
249 
        l.nop
250 
 
251 
        CHECK_CY_SET
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253 
        l.add   r3, r0, r0      ;// Should clear CY
254 
        CHECK_CY_CLEAR
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256 
        // Add with carry and generate carry with l.addic
257 
 
258 
        l.addi  r3, r4, 0x1001
259 
        l.addic r3, r4, 0x1001
260 
        l.nop   0x2
261 
 
262 
        l.sfnei r3, 0x1
263 
        l.bf    _fail
264 
        l.nop
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266 
        CHECK_CY_SET
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268 
_finish:
269 
        l.movhi r3, hi(0x8000000d)
270 
        l.ori   r3, r3, lo(0x8000000d)
271 
        l.nop   0x2
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        l.ori   r3, r0, 0
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        l.nop   0x1
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275 
_fail:
276 
        l.ori   r3, r0, 1
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        l.nop   0x1

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