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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-cy.S] - Blame information for rev 502

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/*
        OR1200 carry bit checking
 
        Carry generated on all adds which we interpret to be
        unsigned. The CPU will generate both CY and OV.
        CY is generated when unsigned values generate an extra bit.
        OV is when the values, interpreted as signed, cannot have
        the result displayed as it is too large.
 
        OV is not checked here. Just CY generation and inclusion by
        the l.addc and l.addic instructions.
 
        Very basic, testing.
 
TODO:    Substraction carry out testing.
 
        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
 
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
        .org 0x600
        l.nop 0x1
 
 
/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
        .org 0x700
#ifndef OR1200_IMPL_ADDC
        // No problem - instruction not supported
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2
        l.ori   r3, r0, 0
#else
        l.ori   r3, r0, 1
#endif
        l.nop   0x1
 
/* ---[ 0xb00: Range exception ]---------------------------------------- */
        .org 0xb00
        l.sw    0(r0), r3
        l.ori   r3, r0, 0xaaee
        l.nop   0x2
        l.lwz   r3, 0(r0)
        l.rfe
 
/* =================================================== [ text ] === */
        .section .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
        // Clear all regs
        l.movhi r1, 0
        l.movhi r2, 0
        l.movhi r3, 0
        l.movhi r4, 0
        l.movhi r5, 0
        l.movhi r6, 0
        l.movhi r7, 0
        l.movhi r8, 0
        l.movhi r9, 0
        l.movhi r10, 0
        l.movhi r11, 0
        l.movhi r12, 0
        l.movhi r13, 0
        l.movhi r14, 0
        l.movhi r15, 0
        l.movhi r16, 0
        l.movhi r17, 0
        l.movhi r18, 0
        l.movhi r19, 0
        l.movhi r20, 0
        l.movhi r21, 0
        l.movhi r22, 0
        l.movhi r23, 0
        l.movhi r24, 0
        l.movhi r25, 0
        l.movhi r26, 0
        l.movhi r27, 0
        l.movhi r28, 0
        l.movhi r29, 0
        l.movhi r30, 0
        l.movhi r31, 0
 
#ifdef OR1200_IMPL_CY
        // Kick off test
        l.jal   _main
#else
        // Not supported, exit test
        l.j     _finish
#endif
        l.nop
 
 
/* =================================================== [ main ] === */
 
 
#define CHECK_CY_CLEAR                  \
        l.mfspr r20, r0, SPR_SR ;       \
        l.andi  r21, r20, SPR_SR_CY ;   \
        l.sfne  r21, r0           ;     \
        l.bf    _fail             ;     \
        l.nop
 
#define CHECK_CY_SET                    \
        l.mfspr r20, r0, SPR_SR ;       \
        l.andi  r21, r20, SPR_SR_CY ;   \
        l.sfnei r21, SPR_SR_CY    ;     \
        l.bf    _fail             ;     \
        l.nop
 
        .global _main
_main:
 
        // Set up some values, check the CY bit is cleared from reset
        CHECK_CY_CLEAR
 
        // A large unsigned value
        l.movhi r4, 0xffff
        l.ori   r4, r4, 0xefff
 
        // A value large enough to cause carry
        l.ori   r5, r0, 0x1001
 
        l.add   r3, r5, r4      ;// Should set CY
        l.nop   0x2
        CHECK_CY_SET
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        l.addi  r3, r4, 0x1001  ;// Should set CY
        l.nop   0x2
        CHECK_CY_SET
 
        l.addi  r3, r4, 0x1000  ;// Shouldn't set CY
        l.nop   0x2
        CHECK_CY_CLEAR
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        // Check use of carry - l.addc
        l.addi  r3, r4, 0x1001  ;// Should set CY
        ;; // Consequtive instructions
        l.addc  r3, r3, r5      ;// r3 should be 0x1002
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x1002
        l.bf    _fail
        l.nop
 
        l.add   r3, r4, r5      ;// Should set CY
        l.nop                   ;// 1 delay instruction
        l.addc  r3, r3, r5      ;// r3 should be 0x1002
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x1002
        l.bf    _fail
        l.nop
 
        l.add   r3, r4, r5      ;// Should set
        l.nop   0x2             ;// 1 delay instruction
        l.nop                   ;// 2nd delay instruction
        l.addc  r3, r3, r5      ;// r3 should be 0x1002
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x1002
        l.bf    _fail
        l.nop
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        // Check use of carry - l.addic
        l.addi  r3, r4, 0x1001  ;// Should set CY
        ;; // Consequtive instructions
        l.addic r3, r3, 0x1     ;// r3 should be 2
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x2
        l.bf    _fail
        l.nop
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        l.add   r3, r4, r5      ;// Should set CY
        l.nop                   ;// 1 delay instruction
        l.addic r3, r3, 0x1     ;// r3 should be 2
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x2
        l.bf    _fail
        l.nop
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        l.add   r3, r4, r5      ;// Should set
        l.nop   0x2             ;// 1 delay instruction
        l.nop                   ;// 2nd delay instruction
        l.addic r3, r3, 0x1     ;// r3 should be 2
        l.nop   0x2             ;// Report
 
        l.sfnei r3, 0x2
        l.bf    _fail
        l.nop
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        // Add with carry and generate carry with l.addc
 
        l.add   r3, r4, r5
        l.addc  r3, r4, r5
        l.nop   0x2
 
        l.sfnei r3, 0x1
        l.bf    _fail
        l.nop
 
        CHECK_CY_SET
 
        l.add   r3, r0, r0      ;// Should clear CY
        CHECK_CY_CLEAR
 
        // Add with carry and generate carry with l.addic
 
        l.addi  r3, r4, 0x1001
        l.addic r3, r4, 0x1001
        l.nop   0x2
 
        l.sfnei r3, 0x1
        l.bf    _fail
        l.nop
 
        CHECK_CY_SET
 
_finish:
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2
        l.ori   r3, r0, 0
        l.nop   0x1
 
_fail:
        l.ori   r3, r0, 1
        l.nop   0x1

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-cy.S] - Blame information for rev 502

Line No.	Rev	Author	Line
1	502	julius	`/*`
2			`OR1200 carry bit checking`
3
4			`Carry generated on all adds which we interpret to be`
5			`unsigned. The CPU will generate both CY and OV.`
6			`CY is generated when unsigned values generate an extra bit.`
7			`OV is when the values, interpreted as signed, cannot have`
8			`the result displayed as it is too large.`
9
10			`OV is not checked here. Just CY generation and inclusion by`
11			`the l.addc and l.addic instructions.`
12
13			`Very basic, testing.`
14
15			`TODO: Substraction carry out testing.`
16
17			`Julius Baxter, ORSoC AB, julius.baxter@orsoc.se`
18
19			`*/`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2011 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46
47
48			`#include "spr-defs.h"`
49			`#include "board.h"`
50			`#include "or1200-defines.h"`
51
52
53			`/* =================================================== [ exceptions ] === */`
54			`.section .vectors, "ax"`
55
56
57			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
58			`.org 0x100`
59			`l.movhi r0, 0`
60			`/* Clear status register */`
61			`l.ori r1, r0, SPR_SR_SM`
62			`l.mtspr r0, r1, SPR_SR`
63			`/* Clear timer */`
64			`l.mtspr r0, r0, SPR_TTMR`
65
66			`/* Jump to program initialisation code */`
67			`.global _start`
68			`l.movhi r4, hi(_start)`
69			`l.ori r4, r4, lo(_start)`
70			`l.jr r4`
71			`l.nop`
72
73			`.org 0x600`
74			`l.nop 0x1`
75
76
77			`/* ---[ 0x700: Illegal instruction exception ]-------------------------- */`
78			`.org 0x700`
79			`#ifndef OR1200_IMPL_ADDC`
80			`// No problem - instruction not supported`
81			`l.movhi r3, hi(0x8000000d)`
82			`l.ori r3, r3, lo(0x8000000d)`
83			`l.nop 0x2`
84			`l.ori r3, r0, 0`
85			`#else`
86			`l.ori r3, r0, 1`
87			`#endif`
88			`l.nop 0x1`
89
90			`/* ---[ 0xb00: Range exception ]---------------------------------------- */`
91			`.org 0xb00`
92			`l.sw 0(r0), r3`
93			`l.ori r3, r0, 0xaaee`
94			`l.nop 0x2`
95			`l.lwz r3, 0(r0)`
96			`l.rfe`
97
98			`/* =================================================== [ text ] === */`
99			`.section .text`
100
101			`/* =================================================== [ start ] === */`
102
103			`.global _start`
104			`_start:`
105			`// Clear all regs`
106			`l.movhi r1, 0`
107			`l.movhi r2, 0`
108			`l.movhi r3, 0`
109			`l.movhi r4, 0`
110			`l.movhi r5, 0`
111			`l.movhi r6, 0`
112			`l.movhi r7, 0`
113			`l.movhi r8, 0`
114			`l.movhi r9, 0`
115			`l.movhi r10, 0`
116			`l.movhi r11, 0`
117			`l.movhi r12, 0`
118			`l.movhi r13, 0`
119			`l.movhi r14, 0`
120			`l.movhi r15, 0`
121			`l.movhi r16, 0`
122			`l.movhi r17, 0`
123			`l.movhi r18, 0`
124			`l.movhi r19, 0`
125			`l.movhi r20, 0`
126			`l.movhi r21, 0`
127			`l.movhi r22, 0`
128			`l.movhi r23, 0`
129			`l.movhi r24, 0`
130			`l.movhi r25, 0`
131			`l.movhi r26, 0`
132			`l.movhi r27, 0`
133			`l.movhi r28, 0`
134			`l.movhi r29, 0`
135			`l.movhi r30, 0`
136			`l.movhi r31, 0`
137
138			`#ifdef OR1200_IMPL_CY`
139			`// Kick off test`
140			`l.jal _main`
141			`#else`
142			`// Not supported, exit test`
143			`l.j _finish`
144			`#endif`
145			`l.nop`
146
147
148			`/* =================================================== [ main ] === */`
149
150
151			`#define CHECK_CY_CLEAR \`
152			`l.mfspr r20, r0, SPR_SR ; \`
153			`l.andi r21, r20, SPR_SR_CY ; \`
154			`l.sfne r21, r0 ; \`
155			`l.bf _fail ; \`
156			`l.nop`
157
158			`#define CHECK_CY_SET \`
159			`l.mfspr r20, r0, SPR_SR ; \`
160			`l.andi r21, r20, SPR_SR_CY ; \`
161			`l.sfnei r21, SPR_SR_CY ; \`
162			`l.bf _fail ; \`
163			`l.nop`
164
165			`.global _main`
166			`_main:`
167
168			`// Set up some values, check the CY bit is cleared from reset`
169			`CHECK_CY_CLEAR`
170
171			`// A large unsigned value`
172			`l.movhi r4, 0xffff`
173			`l.ori r4, r4, 0xefff`
174
175			`// A value large enough to cause carry`
176			`l.ori r5, r0, 0x1001`
177
178			`l.add r3, r5, r4 ;// Should set CY`
179			`l.nop 0x2`
180			`CHECK_CY_SET`
181
182			`l.add r3, r0, r0 ;// Should clear CY`
183			`CHECK_CY_CLEAR`
184
185			`l.addi r3, r4, 0x1001 ;// Should set CY`
186			`l.nop 0x2`
187			`CHECK_CY_SET`
188
189			`l.addi r3, r4, 0x1000 ;// Shouldn't set CY`
190			`l.nop 0x2`
191			`CHECK_CY_CLEAR`
192
193			`l.add r3, r0, r0 ;// Should clear CY`
194			`CHECK_CY_CLEAR`
195
196			`// Check use of carry - l.addc`
197			`l.addi r3, r4, 0x1001 ;// Should set CY`
198			`;; // Consequtive instructions`
199			`l.addc r3, r3, r5 ;// r3 should be 0x1002`
200			`l.nop 0x2 ;// Report`
201
202			`l.sfnei r3, 0x1002`
203			`l.bf _fail`
204			`l.nop`
205
206			`l.add r3, r4, r5 ;// Should set CY`
207			`l.nop ;// 1 delay instruction`
208			`l.addc r3, r3, r5 ;// r3 should be 0x1002`
209			`l.nop 0x2 ;// Report`
210
211			`l.sfnei r3, 0x1002`
212			`l.bf _fail`
213			`l.nop`
214
215			`l.add r3, r4, r5 ;// Should set`
216			`l.nop 0x2 ;// 1 delay instruction`
217			`l.nop ;// 2nd delay instruction`
218			`l.addc r3, r3, r5 ;// r3 should be 0x1002`
219			`l.nop 0x2 ;// Report`
220
221			`l.sfnei r3, 0x1002`
222			`l.bf _fail`
223			`l.nop`
224
225			`l.add r3, r0, r0 ;// Should clear CY`
226			`CHECK_CY_CLEAR`
227
228			`// Check use of carry - l.addic`
229			`l.addi r3, r4, 0x1001 ;// Should set CY`
230			`;; // Consequtive instructions`
231			`l.addic r3, r3, 0x1 ;// r3 should be 2`
232			`l.nop 0x2 ;// Report`
233
234			`l.sfnei r3, 0x2`
235			`l.bf _fail`
236			`l.nop`
237
238			`l.add r3, r0, r0 ;// Should clear CY`
239			`CHECK_CY_CLEAR`
240
241			`l.add r3, r4, r5 ;// Should set CY`
242			`l.nop ;// 1 delay instruction`
243			`l.addic r3, r3, 0x1 ;// r3 should be 2`
244			`l.nop 0x2 ;// Report`
245
246			`l.sfnei r3, 0x2`
247			`l.bf _fail`
248			`l.nop`
249
250			`l.add r3, r0, r0 ;// Should clear CY`
251			`CHECK_CY_CLEAR`
252
253			`l.add r3, r4, r5 ;// Should set`
254			`l.nop 0x2 ;// 1 delay instruction`
255			`l.nop ;// 2nd delay instruction`
256			`l.addic r3, r3, 0x1 ;// r3 should be 2`
257			`l.nop 0x2 ;// Report`
258
259			`l.sfnei r3, 0x2`
260			`l.bf _fail`
261			`l.nop`
262
263			`l.add r3, r0, r0 ;// Should clear CY`
264			`CHECK_CY_CLEAR`
265
266			`// Add with carry and generate carry with l.addc`
267
268			`l.add r3, r4, r5`
269			`l.addc r3, r4, r5`
270			`l.nop 0x2`
271
272			`l.sfnei r3, 0x1`
273			`l.bf _fail`
274			`l.nop`
275
276			`CHECK_CY_SET`
277
278			`l.add r3, r0, r0 ;// Should clear CY`
279			`CHECK_CY_CLEAR`
280
281			`// Add with carry and generate carry with l.addic`
282
283			`l.addi r3, r4, 0x1001`
284			`l.addic r3, r4, 0x1001`
285			`l.nop 0x2`
286
287			`l.sfnei r3, 0x1`
288			`l.bf _fail`
289			`l.nop`
290
291			`CHECK_CY_SET`
292
293			`_finish:`
294			`l.movhi r3, hi(0x8000000d)`
295			`l.ori r3, r3, lo(0x8000000d)`
296			`l.nop 0x2`
297			`l.ori r3, r0, 0`
298			`l.nop 0x1`
299
300			`_fail:`
301			`l.ori r3, r0, 1`
302			`l.nop 0x1`