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/*
        Delay-slot exception bit (DSX) test.
 
        Generate some exceptions in delay slots and not in delay slots
        and confirm the SR[DSX] bit gets set.
 
        Just synchronous exceptions for now (a bit trickier to test
        asynchronous ones like timer and interrupts.)
 
        Set r10 to hold whether we are expecting SR[DSX] to be set or
        not. Exceptions will advance the PC by 0x8 to step over both
        the jump/branch and instruction causing an exception.
 
        Julius Baxter 
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2012 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include "spr-defs.h"
#include "board.h"
 
#define TEST_DSX_AND_RETURN                                                     ; \
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */                           ; \
        l.nop   2                       /* Report PC for diagnostic purpose */  ; \
        /* Check SR[DSX] was as expected */                                     ; \
        l.mfspr r8,r0,SPR_SR            /* Get SR */                            ; \
        l.andi  r8,r8,SPR_SR_DSX        /* Clear all bits except DSX */         ; \
        l.xor   r8,r8,r10               /* r8 will be >0 if error */            ; \
        l.sfne  r8,r0                                                           ; \
        l.bf    test_fail                                                       ; \
        l.nop                                                                   ; \
        /* Check if we were in delay slot, if so just advance by 8, else 4 */   ; \
        l.addi  r3,r3,4                 /* Step two instructions past where     ; \
                                        exception       occurred */             ; \
        l.srli  r8,r10,11               /* If we were in delay slot, add extra  ; \
                                        4 to PC (0x2000>>11=4)*/                ; \
        l.add   r3,r3,r8                                                        ; \
        l.mtspr r0,r3,SPR_EPCR_BASE                                             ; \
        l.rfe
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global stack
        l.movhi r1, hi(stack)
        l.ori   r1, r1, lo(stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* ---[ 0x200: BUS error ]------------------------------------------------ */
        .org 0x200
        .global _bus_handler
_bus_handler:
        TEST_DSX_AND_RETURN
 
 
/* ---[ 0x600: ALIGN error ]------------------------------------------------ */
        .org 0x600
        .global _align_handler
_align_handler:
        TEST_DSX_AND_RETURN
 
 
/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
        .org 0x700
        .global _illinsn_handler
_illinsn_handler:
        TEST_DSX_AND_RETURN
 
/* ---[ 0x900: DTLB exception ]--------------------------------------------- */
        .org 0x900
        .global _dtlb_handler
        TEST_DSX_AND_RETURN
 
/* ---[ 0xe00: TRAP error ]------------------------------------------------ */
        .org 0xe00
        .global _trap_handler
_trap_handler:
        TEST_DSX_AND_RETURN
 
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
        /* r2 is test counter - put in r3 and will be printed out for each
        successful call to test_func */
        l.movhi r2,0
 
        l.movhi r9,hi(test_fail)
        l.ori   r9,r9,lo(test_fail)
 
        /* Alignment exception tests */
 
        /* This test should _NOT_ set DSX, so clear r10 */
        l.movhi r10,0
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfeq  r0,r0
        l.bf    test_func
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfne  r0,r0
        l.bnf   test_func
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.j     test_func
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.jal   test_func
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jr    r5
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jalr  r5
        /* Should cause an alignment error */
        l.lwz   r1,1(r0)
 
        /* Make some calls to the functions which will trigger exceptions
           to check that the DSX bit is not set */
        l.ori   r10,r0,0
        l.jal   align_func
        l.nop
 
 
        /* Illegal instruction exception tests */
 
        /* This test should _NOT_ set DSX, so clear r10 */
        l.movhi r10,0
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfeq  r0,r0
        l.bf    test_func
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfne  r0,r0
        l.bnf   test_func
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.j     test_func
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.jal   test_func
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jr    r5
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jalr  r5
        /* Should cause an illegal insn error */
        .word 0xef000000
 
        /* Make some calls to the functions which will trigger exceptions
           to check that the DSX bit is not set */
        l.ori   r10,r0,0
        l.jal   illegal_insn_func
        l.nop
 
        /* Bus error exceptions */
 
        /* This test should _NOT_ set DSX, so clear r10 */
        l.movhi r10,0
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfeq  r0,r0
        l.bf    test_func
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfne  r0,r0
        l.bnf   test_func
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.j     test_func
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.jal   test_func
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jr    r5
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jalr  r5
        /* This should cause a bus error */
        l.lwz   r1,-4(r0)
 
        /* Make some calls to the functions which will trigger exceptions
           to check that the DSX bit is not set */
        l.ori   r10,r0,0
        l.jal   bus_err_func
        l.nop
 
        /* Trap instruction exception tests */
 
        /* This test should _NOT_ set DSX, so clear r10 */
        l.movhi r10,0
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfeq  r0,r0
        l.bf    test_func
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfne  r0,r0
        l.bnf   test_func
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.j     test_func
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.jal   test_func
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jr    r5
        /* Should cause an trap error */
        l.trap 0
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jalr  r5
        /* Should cause an trap error */
        l.trap 0
 
        /* Make some calls to the functions which will trigger exceptions
           to check that the DSX bit is not set */
        l.ori   r10,r0,0
        l.jal   trap_func
        l.nop
 
        /* DMMU miss test */
 
        /* Check if we have a DMMU */
        l.mfspr r3,r0,SPR_UPR
        l.andi  r3,r3,SPR_UPR_DMP
        l.sfeq  r3,r0
        /* Flag set if no DMMU */
        l.bf    dmmu_test_done
        l.nop
 
        /* Just enabling the DMMU with no valid match match registers should
        be enough to determine number of DMMU entries - hold this value in r3 */
        l.mfspr r3,r0,SPR_DMMUCFGR
        l.andi  r4,r3,SPR_DMMUCFGR_NTS
        l.srli  r4,r4,SPR_DMMUCFGR_NTS_OFF
        l.ori   r6,r0,1
        l.sll   r3,r6,r4
 
        /* Setup the Data MMU's TLBS - invalidate them */
        l.movhi r4, hi(SPR_DTLBMR_BASE(0))
        l.ori r4, r4, lo(SPR_DTLBMR_BASE(0))
 
        /* DTLB invalidate loop */
1:
        l.mtspr r4, r0, 0x0
        l.addi r4, r4, 0x1
        l.sfeq r3, r0
        l.bnf 1b
        l.addi r3, r3, -1
 
        .extern lo_dmmu_en
        /* Now enable the DMMU */
        l.movhi r4, hi(lo_dmmu_en)
        l.ori r4, r4, lo(lo_dmmu_en)
        l.jalr r4
        l.nop
 
        /* Now any data access should cause a miss */
 
        /* This test should _NOT_ set DSX, so clear r10 */
        l.movhi r10,0
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfeq  r0,r0
        l.bf    test_func
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.sfne  r0,r0
        l.bnf   test_func
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.j     test_func
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.jal   test_func
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jr    r5
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* This test should_ set DSX, so put SPR_SR_DSX in r10 */
        l.ori   r10,r0,SPR_SR_DSX
        l.movhi r5,hi(test_func)
        l.ori   r5,r5,lo(test_func)
        l.jalr  r5
        /* This should cause a DLTB miss */
        l.lwz   r1,0(r0)
 
        /* Make some calls to the functions which will trigger exceptions
           to check that the DSX bit is not set */
        l.ori   r10,r0,0
        l.jal   dtlb_func
        l.nop
 
        /* Now disable DMMU */
        l.mfspr r3,r0,SPR_SR
        l.xori  r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.movhi r9,hi(dmmu_test_done)
        l.ori   r9,r9,lo(dmmu_test_done)
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
 
dmmu_test_done:
 
        /* Check if we have an instruction cache */
        l.mfspr r3,r0,SPR_UPR
        l.andi  r3,r3,SPR_UPR_ICP
        l.sfeq  r3,r0
        /* Flag set if no icache */
        l.bf    test_ok
        l.nop
 
        /* Now repeat the tests with caches enabled if they weren't */
        l.mfspr r1,r0,SPR_SR
        l.andi  r1,r1,SPR_SR_ICE
        l.sfeq  r0,r1  /* Set flag if caches not enabled */
        l.bf    restart_with_caches_enabled
        l.nop
 
test_ok:
        l.movhi r3,0x8000
        l.ori   r3,r3,0x000d
        l.nop   2
        l.or    r3,r0,r0
        l.nop   1
 
test_func:
        /* A test function to call, just return */
        l.jr    r9
        l.nop   2       /* print out whatever is in r3 */
 
test_fail:
        l.movhi r3,0xbaaa
        l.ori   r3,r3,0xaaad
        l.nop   2
        l.ori   r3,r0,1
        l.nop   1
 
align_func:
        /* DSX should _not_ be set on exception here */
        l.lwz   r1,1(r0)
        l.jr    r9
        l.nop
 
illegal_insn_func:
        /* DSX should _not_ be set on exception here */
        .word 0xef000000
        l.jr    r9
        l.nop
 
bus_err_func:
        /* DSX should _not_ be set on exception here */
        l.lwz   r1,-4(r0)
        l.jr    r9
        l.nop
 
trap_func:
        /* DSX should _not_ be set on exception here */
        l.trap  0
        l.jr    r9
        l.nop
 
dtlb_func:
        /* DSX should _not_ be set on exception here */
        l.lwz   r1,0(r0)
        l.jr    r9
        l.nop
 
restart_with_caches_enabled:
        l.jal   _cache_init
        l.nop
        l.j     _start
        l.nop

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-dsx.S] - Blame information for rev 807

Line No.	Rev	Author	Line
1	807	julius	`/*`
2			`Delay-slot exception bit (DSX) test.`
3
4			`Generate some exceptions in delay slots and not in delay slots`
5			`and confirm the SR[DSX] bit gets set.`
6
7			`Just synchronous exceptions for now (a bit trickier to test`
8			`asynchronous ones like timer and interrupts.)`
9
10			`Set r10 to hold whether we are expecting SR[DSX] to be set or`
11			`not. Exceptions will advance the PC by 0x8 to step over both`
12			`the jump/branch and instruction causing an exception.`
13
14			`Julius Baxter`
15
16			`*/`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2012 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`#include "spr-defs.h"`
45			`#include "board.h"`
46
47			`#define TEST_DSX_AND_RETURN ; \`
48			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPC */ ; \`
49			`l.nop 2 /* Report PC for diagnostic purpose */ ; \`
50			`/* Check SR[DSX] was as expected */ ; \`
51			`l.mfspr r8,r0,SPR_SR /* Get SR */ ; \`
52			`l.andi r8,r8,SPR_SR_DSX /* Clear all bits except DSX */ ; \`
53			`l.xor r8,r8,r10 /* r8 will be >0 if error */ ; \`
54			`l.sfne r8,r0 ; \`
55			`l.bf test_fail ; \`
56			`l.nop ; \`
57			`/* Check if we were in delay slot, if so just advance by 8, else 4 */ ; \`
58			`l.addi r3,r3,4 /* Step two instructions past where ; \`
59			`exception occurred */ ; \`
60			`l.srli r8,r10,11 /* If we were in delay slot, add extra ; \`
61			`4 to PC (0x2000>>11=4)*/ ; \`
62			`l.add r3,r3,r8 ; \`
63			`l.mtspr r0,r3,SPR_EPCR_BASE ; \`
64			`l.rfe`
65
66
67			`/* =================================================== [ exceptions ] === */`
68			`.section .vectors, "ax"`
69
70
71			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
72			`.org 0x100`
73			`l.movhi r0, 0`
74			`/* Clear status register */`
75			`l.ori r1, r0, SPR_SR_SM`
76			`l.mtspr r0, r1, SPR_SR`
77			`/* Clear timer */`
78			`l.mtspr r0, r0, SPR_TTMR`
79			`/* Init the stack */`
80			`.global stack`
81			`l.movhi r1, hi(stack)`
82			`l.ori r1, r1, lo(stack)`
83			`l.addi r2, r0, -3`
84			`l.and r1, r1, r2`
85			`/* Jump to program initialisation code */`
86			`.global _start`
87			`l.movhi r4, hi(_start)`
88			`l.ori r4, r4, lo(_start)`
89			`l.jr r4`
90			`l.nop`
91
92
93			`/* ---[ 0x200: BUS error ]------------------------------------------------ */`
94			`.org 0x200`
95			`.global _bus_handler`
96			`_bus_handler:`
97			`TEST_DSX_AND_RETURN`
98
99
100			`/* ---[ 0x600: ALIGN error ]------------------------------------------------ */`
101			`.org 0x600`
102			`.global _align_handler`
103			`_align_handler:`
104			`TEST_DSX_AND_RETURN`
105
106
107			`/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */`
108			`.org 0x700`
109			`.global _illinsn_handler`
110			`_illinsn_handler:`
111			`TEST_DSX_AND_RETURN`
112
113			`/* ---[ 0x900: DTLB exception ]--------------------------------------------- */`
114			`.org 0x900`
115			`.global _dtlb_handler`
116			`TEST_DSX_AND_RETURN`
117
118			`/* ---[ 0xe00: TRAP error ]------------------------------------------------ */`
119			`.org 0xe00`
120			`.global _trap_handler`
121			`_trap_handler:`
122			`TEST_DSX_AND_RETURN`
123
124
125			`/* =================================================== [ text section ] === */`
126			`.section .text`
127
128			`/* =================================================== [ start ] === */`
129
130			`.global _start`
131			`_start:`
132			`/* r2 is test counter - put in r3 and will be printed out for each`
133			`successful call to test_func */`
134			`l.movhi r2,0`
135
136			`l.movhi r9,hi(test_fail)`
137			`l.ori r9,r9,lo(test_fail)`
138
139			`/* Alignment exception tests */`
140
141			`/* This test should _NOT_ set DSX, so clear r10 */`
142			`l.movhi r10,0`
143			`/* Should cause an alignment error */`
144			`l.lwz r1,1(r0)`
145
146			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
147			`l.ori r10,r0,SPR_SR_DSX`
148			`l.sfeq r0,r0`
149			`l.bf test_func`
150			`/* Should cause an alignment error */`
151			`l.lwz r1,1(r0)`
152
153			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
154			`l.ori r10,r0,SPR_SR_DSX`
155			`l.sfne r0,r0`
156			`l.bnf test_func`
157			`/* Should cause an alignment error */`
158			`l.lwz r1,1(r0)`
159
160			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
161			`l.ori r10,r0,SPR_SR_DSX`
162			`l.j test_func`
163			`/* Should cause an alignment error */`
164			`l.lwz r1,1(r0)`
165
166			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
167			`l.ori r10,r0,SPR_SR_DSX`
168			`l.jal test_func`
169			`/* Should cause an alignment error */`
170			`l.lwz r1,1(r0)`
171
172			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
173			`l.ori r10,r0,SPR_SR_DSX`
174			`l.movhi r5,hi(test_func)`
175			`l.ori r5,r5,lo(test_func)`
176			`l.jr r5`
177			`/* Should cause an alignment error */`
178			`l.lwz r1,1(r0)`
179
180			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
181			`l.ori r10,r0,SPR_SR_DSX`
182			`l.movhi r5,hi(test_func)`
183			`l.ori r5,r5,lo(test_func)`
184			`l.jalr r5`
185			`/* Should cause an alignment error */`
186			`l.lwz r1,1(r0)`
187
188			`/* Make some calls to the functions which will trigger exceptions`
189			`to check that the DSX bit is not set */`
190			`l.ori r10,r0,0`
191			`l.jal align_func`
192			`l.nop`
193
194
195			`/* Illegal instruction exception tests */`
196
197			`/* This test should _NOT_ set DSX, so clear r10 */`
198			`l.movhi r10,0`
199			`/* Should cause an illegal insn error */`
200			`.word 0xef000000`
201
202			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
203			`l.ori r10,r0,SPR_SR_DSX`
204			`l.sfeq r0,r0`
205			`l.bf test_func`
206			`/* Should cause an illegal insn error */`
207			`.word 0xef000000`
208
209			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
210			`l.ori r10,r0,SPR_SR_DSX`
211			`l.sfne r0,r0`
212			`l.bnf test_func`
213			`/* Should cause an illegal insn error */`
214			`.word 0xef000000`
215
216			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
217			`l.ori r10,r0,SPR_SR_DSX`
218			`l.j test_func`
219			`/* Should cause an illegal insn error */`
220			`.word 0xef000000`
221
222			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
223			`l.ori r10,r0,SPR_SR_DSX`
224			`l.jal test_func`
225			`/* Should cause an illegal insn error */`
226			`.word 0xef000000`
227
228			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
229			`l.ori r10,r0,SPR_SR_DSX`
230			`l.movhi r5,hi(test_func)`
231			`l.ori r5,r5,lo(test_func)`
232			`l.jr r5`
233			`/* Should cause an illegal insn error */`
234			`.word 0xef000000`
235
236			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
237			`l.ori r10,r0,SPR_SR_DSX`
238			`l.movhi r5,hi(test_func)`
239			`l.ori r5,r5,lo(test_func)`
240			`l.jalr r5`
241			`/* Should cause an illegal insn error */`
242			`.word 0xef000000`
243
244			`/* Make some calls to the functions which will trigger exceptions`
245			`to check that the DSX bit is not set */`
246			`l.ori r10,r0,0`
247			`l.jal illegal_insn_func`
248			`l.nop`
249
250			`/* Bus error exceptions */`
251
252			`/* This test should _NOT_ set DSX, so clear r10 */`
253			`l.movhi r10,0`
254			`/* This should cause a bus error */`
255			`l.lwz r1,-4(r0)`
256
257			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
258			`l.ori r10,r0,SPR_SR_DSX`
259			`l.sfeq r0,r0`
260			`l.bf test_func`
261			`/* This should cause a bus error */`
262			`l.lwz r1,-4(r0)`
263
264			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
265			`l.ori r10,r0,SPR_SR_DSX`
266			`l.sfne r0,r0`
267			`l.bnf test_func`
268			`/* This should cause a bus error */`
269			`l.lwz r1,-4(r0)`
270
271			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
272			`l.ori r10,r0,SPR_SR_DSX`
273			`l.j test_func`
274			`/* This should cause a bus error */`
275			`l.lwz r1,-4(r0)`
276
277			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
278			`l.ori r10,r0,SPR_SR_DSX`
279			`l.jal test_func`
280			`/* This should cause a bus error */`
281			`l.lwz r1,-4(r0)`
282
283			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
284			`l.ori r10,r0,SPR_SR_DSX`
285			`l.movhi r5,hi(test_func)`
286			`l.ori r5,r5,lo(test_func)`
287			`l.jr r5`
288			`/* This should cause a bus error */`
289			`l.lwz r1,-4(r0)`
290
291			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
292			`l.ori r10,r0,SPR_SR_DSX`
293			`l.movhi r5,hi(test_func)`
294			`l.ori r5,r5,lo(test_func)`
295			`l.jalr r5`
296			`/* This should cause a bus error */`
297			`l.lwz r1,-4(r0)`
298
299			`/* Make some calls to the functions which will trigger exceptions`
300			`to check that the DSX bit is not set */`
301			`l.ori r10,r0,0`
302			`l.jal bus_err_func`
303			`l.nop`
304
305			`/* Trap instruction exception tests */`
306
307			`/* This test should _NOT_ set DSX, so clear r10 */`
308			`l.movhi r10,0`
309			`/* Should cause an trap error */`
310			`l.trap 0`
311
312			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
313			`l.ori r10,r0,SPR_SR_DSX`
314			`l.sfeq r0,r0`
315			`l.bf test_func`
316			`/* Should cause an trap error */`
317			`l.trap 0`
318
319			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
320			`l.ori r10,r0,SPR_SR_DSX`
321			`l.sfne r0,r0`
322			`l.bnf test_func`
323			`/* Should cause an trap error */`
324			`l.trap 0`
325
326			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
327			`l.ori r10,r0,SPR_SR_DSX`
328			`l.j test_func`
329			`/* Should cause an trap error */`
330			`l.trap 0`
331
332			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
333			`l.ori r10,r0,SPR_SR_DSX`
334			`l.jal test_func`
335			`/* Should cause an trap error */`
336			`l.trap 0`
337
338			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
339			`l.ori r10,r0,SPR_SR_DSX`
340			`l.movhi r5,hi(test_func)`
341			`l.ori r5,r5,lo(test_func)`
342			`l.jr r5`
343			`/* Should cause an trap error */`
344			`l.trap 0`
345
346			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
347			`l.ori r10,r0,SPR_SR_DSX`
348			`l.movhi r5,hi(test_func)`
349			`l.ori r5,r5,lo(test_func)`
350			`l.jalr r5`
351			`/* Should cause an trap error */`
352			`l.trap 0`
353
354			`/* Make some calls to the functions which will trigger exceptions`
355			`to check that the DSX bit is not set */`
356			`l.ori r10,r0,0`
357			`l.jal trap_func`
358			`l.nop`
359
360			`/* DMMU miss test */`
361
362			`/* Check if we have a DMMU */`
363			`l.mfspr r3,r0,SPR_UPR`
364			`l.andi r3,r3,SPR_UPR_DMP`
365			`l.sfeq r3,r0`
366			`/* Flag set if no DMMU */`
367			`l.bf dmmu_test_done`
368			`l.nop`
369
370			`/* Just enabling the DMMU with no valid match match registers should`
371			`be enough to determine number of DMMU entries - hold this value in r3 */`
372			`l.mfspr r3,r0,SPR_DMMUCFGR`
373			`l.andi r4,r3,SPR_DMMUCFGR_NTS`
374			`l.srli r4,r4,SPR_DMMUCFGR_NTS_OFF`
375			`l.ori r6,r0,1`
376			`l.sll r3,r6,r4`
377
378			`/* Setup the Data MMU's TLBS - invalidate them */`
379			`l.movhi r4, hi(SPR_DTLBMR_BASE(0))`
380			`l.ori r4, r4, lo(SPR_DTLBMR_BASE(0))`
381
382			`/* DTLB invalidate loop */`
383			`1:`
384			`l.mtspr r4, r0, 0x0`
385			`l.addi r4, r4, 0x1`
386			`l.sfeq r3, r0`
387			`l.bnf 1b`
388			`l.addi r3, r3, -1`
389
390			`.extern lo_dmmu_en`
391			`/* Now enable the DMMU */`
392			`l.movhi r4, hi(lo_dmmu_en)`
393			`l.ori r4, r4, lo(lo_dmmu_en)`
394			`l.jalr r4`
395			`l.nop`
396
397			`/* Now any data access should cause a miss */`
398
399			`/* This test should _NOT_ set DSX, so clear r10 */`
400			`l.movhi r10,0`
401			`/* This should cause a DLTB miss */`
402			`l.lwz r1,0(r0)`
403
404			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
405			`l.ori r10,r0,SPR_SR_DSX`
406			`l.sfeq r0,r0`
407			`l.bf test_func`
408			`/* This should cause a DLTB miss */`
409			`l.lwz r1,0(r0)`
410
411			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
412			`l.ori r10,r0,SPR_SR_DSX`
413			`l.sfne r0,r0`
414			`l.bnf test_func`
415			`/* This should cause a DLTB miss */`
416			`l.lwz r1,0(r0)`
417
418			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
419			`l.ori r10,r0,SPR_SR_DSX`
420			`l.j test_func`
421			`/* This should cause a DLTB miss */`
422			`l.lwz r1,0(r0)`
423
424			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
425			`l.ori r10,r0,SPR_SR_DSX`
426			`l.jal test_func`
427			`/* This should cause a DLTB miss */`
428			`l.lwz r1,0(r0)`
429
430			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
431			`l.ori r10,r0,SPR_SR_DSX`
432			`l.movhi r5,hi(test_func)`
433			`l.ori r5,r5,lo(test_func)`
434			`l.jr r5`
435			`/* This should cause a DLTB miss */`
436			`l.lwz r1,0(r0)`
437
438			`/* This test should_ set DSX, so put SPR_SR_DSX in r10 */`
439			`l.ori r10,r0,SPR_SR_DSX`
440			`l.movhi r5,hi(test_func)`
441			`l.ori r5,r5,lo(test_func)`
442			`l.jalr r5`
443			`/* This should cause a DLTB miss */`
444			`l.lwz r1,0(r0)`
445
446			`/* Make some calls to the functions which will trigger exceptions`
447			`to check that the DSX bit is not set */`
448			`l.ori r10,r0,0`
449			`l.jal dtlb_func`
450			`l.nop`
451
452			`/* Now disable DMMU */`
453			`l.mfspr r3,r0,SPR_SR`
454			`l.xori r3,r3,SPR_SR_DME`
455			`l.mtspr r0,r3,SPR_ESR_BASE`
456			`l.movhi r9,hi(dmmu_test_done)`
457			`l.ori r9,r9,lo(dmmu_test_done)`
458			`l.mtspr r0,r9,SPR_EPCR_BASE`
459			`l.rfe`
460
461			`dmmu_test_done:`
462
463			`/* Check if we have an instruction cache */`
464			`l.mfspr r3,r0,SPR_UPR`
465			`l.andi r3,r3,SPR_UPR_ICP`
466			`l.sfeq r3,r0`
467			`/* Flag set if no icache */`
468			`l.bf test_ok`
469			`l.nop`
470
471			`/* Now repeat the tests with caches enabled if they weren't */`
472			`l.mfspr r1,r0,SPR_SR`
473			`l.andi r1,r1,SPR_SR_ICE`
474			`l.sfeq r0,r1 /* Set flag if caches not enabled */`
475			`l.bf restart_with_caches_enabled`
476			`l.nop`
477
478			`test_ok:`
479			`l.movhi r3,0x8000`
480			`l.ori r3,r3,0x000d`
481			`l.nop 2`
482			`l.or r3,r0,r0`
483			`l.nop 1`
484
485			`test_func:`
486			`/* A test function to call, just return */`
487			`l.jr r9`
488			`l.nop 2 /* print out whatever is in r3 */`
489
490			`test_fail:`
491			`l.movhi r3,0xbaaa`
492			`l.ori r3,r3,0xaaad`
493			`l.nop 2`
494			`l.ori r3,r0,1`
495			`l.nop 1`
496
497			`align_func:`
498			`/* DSX should _not_ be set on exception here */`
499			`l.lwz r1,1(r0)`
500			`l.jr r9`
501			`l.nop`
502
503			`illegal_insn_func:`
504			`/* DSX should _not_ be set on exception here */`
505			`.word 0xef000000`
506			`l.jr r9`
507			`l.nop`
508
509			`bus_err_func:`
510			`/* DSX should _not_ be set on exception here */`
511			`l.lwz r1,-4(r0)`
512			`l.jr r9`
513			`l.nop`
514
515			`trap_func:`
516			`/* DSX should _not_ be set on exception here */`
517			`l.trap 0`
518			`l.jr r9`
519			`l.nop`
520
521			`dtlb_func:`
522			`/* DSX should _not_ be set on exception here */`
523			`l.lwz r1,0(r0)`
524			`l.jr r9`
525			`l.nop`
526
527			`restart_with_caches_enabled:`
528			`l.jal _cache_init`
529			`l.nop`
530			`l.j _start`
531			`l.nop`