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/*
        Exception test.
 
        The following list outlines the tests performed
 
        Execption test
        - 0x100 reset                        - start addr after reset
        - 0x200 bus error                    - unimplemented addr is accessed
        - 0x300 data page fault              - NOT tested here
        - 0x400 instruction page fault       - NOT tested here
        - 0x500 tick timer                   - NOT tested here
        - 0x600 alignment                    - write to unaligned addr
        - 0x700 illegal instruction          - use unimplemented inst. l.div
        - 0x800 external interrupt           - int triggered from wb slave
        - 0x900 d-tlb miss                   - translation tests
        - 0xA00 i-tlb miss                   - NOT tested here
        - 0xB00 range                        - NOT tested here
        - 0xC00 system call                  - NOT tested here
        - 0xD00 floating point               - NOT tested here
        - 0xE00 trap                         - NOT tested here
        - 0xF00 RESERVED
 
        r11 - 1st exception counter incremented inside exception
        r12 - 2nd exception counter incremented outside and rigth after
              exception
        ... other register use to be documented...
 
        Julius Baxter, julius@opencores.org
        Tadej Markovic, tadej@opencores.org
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global stack
        l.movhi r1, hi(stack)
        l.ori   r1, r1, lo(stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* ---[ 0x200: BUS error ]------------------------------------------------ */
        .org 0x200
        .global _bus_handler
_bus_handler:
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
        l.nop   2
        l.mfspr r3,r0,SPR_EEAR_BASE     /* Get EEA */
        l.nop   2
        l.addi  r11,r11,1               /* Increment 1st exception counter */
        l.sfeqi r30, 0xd /* Is this a data bus test, if so return with l.rfe */
        l.bf 1f
        l.movhi r5, 0    /* r5 should be the one causing the error on dbus */
        /* Instruction bus error test return */
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
        l.ori r5, r5, lo(0x44004800)
        l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
        l.movhi r5,0x1500       /* Put a "l.nop"  instruction in r5 */
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
        l.mtspr r0,r0,SPR_EPCR_BASE     /* RFE to 0x0, which is l.jr r9 */
1:      l.rfe
 
/* ---[ 0x600: ALIGN error ]------------------------------------------------ */
        .org 0x600
        .global _align_handler
_align_handler:
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
        l.nop   2
        l.addi  r11,r11,1               /* Increment 1st exception counter */
        l.movhi r5,0                    /* Clear the pointer register */
        l.rfe
 
 
/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
        .org 0x700
        .global _illinsn_handler
_illinsn_handler:
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
        l.nop   2
        l.addi  r11,r11,1               /* Increment 1st exception counter */
        /* Delay slot test needs this instruction "fixed" */
        l.movhi r5,0x1500               /* Put a "l.nop"  instruction in r5 */
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
        l.mtspr r0,r0,SPR_EPCR_BASE     /* Jump to 0, which is l.jr r9 */
        l.rfe
 
/* ---[ 0x900: DTLB exception ]--------------------------------------------- */
        .org 0x900
        .global _dtlb_handler
/* Exception handler - DMMU TLB miss */
/* Assume 64-entry TLB cache */
_dtlb_handler:
        l.mfspr r20, r0, SPR_EEAR_BASE
        /* Find the entry/set for this address */
        l.srli r21, r20, 13 /* r21 = VPN, shift by size 8192 = 2**13 */
        l.andi r22, r21, 0x3f /* 64 entries = 6 bit mask, r22 = set number */
        /* If page is in the 0xc0000000 space we map to 16MB part of
        memory, ie 0x0 => 0x01000000, otherwise 1-1 mapping */
        l.movhi r23, hi(0xc0000000)
        l.ori r23, r23, lo(0xc0000000)
        l.srli r23, r23, 13 /* Get page address, shift by page size, 13 bits */
        l.movhi r24, hi(0xff << 11) /* Mask for top byte of VPN */
        l.ori r24, r24, lo(0xff << 11)
        l.and r24, r24, r21 /* Mask in only top byte of VPN */
        l.sfeq r23, r24 /* Decide if it's in our special mapped region or not*/
 
        /* First, Setup value for DTLBM (match) reg, is same for both cases */
        l.movhi r24, hi(SPR_ITLBMR_VPN) /* VPN mask into r24 */
        l.ori r24, r24, lo(SPR_ITLBMR_VPN)
        l.and r25, r20, r24 /* AND address with VPN mask */
        l.ori r25, r25, SPR_DTLBMR_V /* OR in valid bit */
        l.mtspr r22, r25, SPR_DTLBMR_BASE(0) /* Write to DTLBR register */
 
        l.bf _highmem_map
        l.nop
 
_lomem_map:
        /* Do 1:1 mapping for this request */
        /* Setup value for translate register */
        l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */
        l.ori r24, r24, lo(SPR_ITLBTR_PPN)
        l.and r25, r20, r24 /* AND address with PPN mask */
        l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
        l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
        l.j _dtlb_done
        l.addi r18, r18, 1 /* Incremement low-mapping counter */
 
_highmem_map:
        /* Do top byte, 0xc0->0x01, mapping for this request */
        /* Setup value for translate register */
        l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */
        l.ori r24, r24, lo(SPR_ITLBTR_PPN)
        l.and r25, r20, r24 /* AND address with PPN mask */
        l.movhi r26, hi(0xff000000) /* Top byte address mask */
        l.or r25, r26, r25 /* Set top byte to 0xff */
        l.xor r25, r26, r25 /* Now clear top byte with XOR */
        l.movhi r26, hi(0x01000000) /* Top address byte */
        l.or r25, r26, r25 /* Set top address byte */
        l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
        l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
        l.addi r19, r19, 1 /* Incremement low-mapping counter */
 
_dtlb_done:
 
        l.rfe
 
 
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
.L10:
        // Kick off test
        l.jal   _main
        l.nop
 
/* ========================================================= [ main ] === */
 
        .global _main
        .global _dmmu_invalidate
        .global _dmmu_except1
 
_main:
        l.nop
        l.addi  r3,r0,0
        l.addi  r5,r0,0
        l.addi  r11,r0,0 /* exception counter 1 */
        l.addi  r12,r0,0 /* exception counter 2 */
        l.addi  r13,r0,0
        l.addi  r18,r0,0 /* DMMU exception counter for low mem mapping */
        l.addi  r19,r0,0 /* DMMU exception counter for hi mem mapping */
        l.sw    0x0(r0),r0      /* Initialize RAM */
        l.sw    0x4(r0),r0      /* Initialize RAM */
        l.sw    0x8(r0),r0      /* Initialize RAM */
        l.sw    0xc(r0),r0      /* Initialize RAM */
        l.sw    0x10(r0),r0     /* Initialize RAM */
        l.sw    0x14(r0),r0     /* Initialize RAM */
        l.sw    0x18(r0),r0     /* Initialize RAM */
        l.sw    0x1c(r0),r0     /* Initialize RAM */
        l.sw    0x20(r0),r0     /* Initialize RAM */
        l.sw    0x24(r0),r0     /* Initialize RAM */
        l.sw    0x28(r0),r0     /* Initialize RAM */
        l.sw    0x2c(r0),r0     /* Initialize RAM */
        l.sw    0x30(r0),r0     /* Initialize RAM */
        l.sw    0x34(r0),r0     /* Initialize RAM */
        l.sw    0x38(r0),r0     /* Initialize RAM */
        l.sw    0x3c(r0),r0     /* Initialize RAM */
        l.sw    0x40(r0),r0     /* Initialize RAM */
        l.sw    0x44(r0),r0     /* Initialize RAM */
        l.sw    0x48(r0),r0     /* Initialize RAM */
        l.sw    0x4c(r0),r0     /* Initialize RAM */
        l.j     _align1
        //l.j _dmmu_except1
        l.nop
 
 
        /* Exceptions followed by NOPs */
 
        /* SW alignment exception */
_align1:
        l.movhi r11,0
        l.nop
        /* Test l.sh */
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.sh 0x0(r5),r0
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.sh 0x0(r5),r0
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        /* Test l.lhz */
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.lhz r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.lhz r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        /* Test l.lhs */
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.lhs r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.lhs r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        /* Test l.sw */
        l.ori r5,r0,0x1 /* Word access, offset 1 */
        l.sw 0x0(r5), r0
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x2 /* Word access, offset 2 */
        l.sw 0x0(r5), r0
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Word access, offset 3 */
        l.sw 0x0(r5), r0
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        /* Test l.lwz */
        l.ori r5,r0,0x1 /* Word access, offset 1 */
        l.lwz r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x2 /* Word access, offset 2 */
        l.lwz r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Word access, offset 3 */
        l.lwz r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
#if OR1200_HAS_LWS==1
        /* Test l.lws */
        l.ori r5,r0,0x1 /* Word access, offset 1 */
        l.lws r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x2 /* Word access, offset 2 */
        l.lws r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Word access, offset 3 */
        l.lws r3,0x0(r5)
        l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.nop
#endif
        /* Now test them in delay slots */
 
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.j 1f
        l.sh 0x0(r5),r0
        l.nop
1:      l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.j 2f
        l.sh 0x0(r5),r0
        l.nop
2:      l.addi r12,r12,1 /* Increment 2nd exception counter */
 
        /* Test l.lhz */
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.j 3f
        l.lhz r3,0x0(r5)
        l.nop
3:      l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.j 4f
        l.lhz r3,0x0(r5)
        l.nop
4:      l.addi r12,r12,1 /* Increment 2nd exception counter */
 
        /* Test l.lhs */
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
        l.j 5f
        l.lhs r3,0x0(r5)
        l.nop
5:      l.addi r12,r12,1 /* Increment 2nd exception counter */
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
        l.j 6f
        l.lhs r3,0x0(r5)
        l.nop
6:      l.addi r12,r12,1 /* Increment 2nd exception counter */
 
        /* Test l.sw */
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
        l.j     7f
        l.sw    0x0(r5), r0
        l.nop
7:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
        l.j     8f
        l.sw    0x0(r5), r0
        l.nop
8:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
        l.j     9f
        l.sh    0x0(r5), r0
        l.nop
9:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
 
        /* Test l.lwz */
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
        l.j     10f
        l.lwz   r3,0x0(r5)
        l.nop
10:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
        l.j     11f
        l.lwz   r3,0x0(r5)
        l.nop
11:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
        l.j     12f
        l.lwz   r3,0x0(r5)
        l.nop
12:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
#if OR1200_HAS_LWS==1
        /* Test l.lws */
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
        l.j     13f
        l.lws   r3,0x0(r5)
        l.nop
13:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
        l.j     14f
        l.lws   r3,0x0(r5)
        l.nop
14:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
        l.j     15f
        l.lws   r3,0x0(r5)
        l.nop
15:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
 
#endif
        /* Check 1st and 2nd exception counters are equal */
        l.sfeq  r11,r12                 /* Should be equal */
        l.bf    17f
        l.nop
        l.nop   1
17:     l.nop   2
        l.nop
 
        /* Illegal instruction exception */
_illegal1:
        l.nop
        l.nop
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
        l.ori   r5, r5, lo(0x44004800)
        l.sw    0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
        l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        /* Call 0x4, illegal opcode instruction */
        l.ori   r6, r0, 0x4
        l.jalr  r6 /* Jump to address 0x4, landing on an illegal instruction */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.nop /* Should return here */
        l.nop
 
        /* Test in delay slot */
 
        l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
        l.sw    0x4(r0), r5   /* Write illegal instruction to RAM addr 0x4 */
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
        l.jalr  r0 /* Jump to address 0, will be a jump back but with an illegal
                     dslot instruction which will befixed by handler */
        l.addi  r12,r12,1 /* Increment 2nd exception counter */
        l.nop /* Should return here */
 
        /* Check 1st and 2nd exception counters are equal */
        l.sfeq  r11,r12                 /* Should be equal */
        l.bf    1f
        l.nop
        l.or    r3, r12, r12
        l.nop   2 /* Report expected exception count */
        l.or    r3, r11, r11
        l.nop   2 /* Report actual exception count */
        l.nop   1
1:      l.nop
        l.nop
 
 
_dbus1:
        l.nop
        l.movhi r12, 0 /* Reset exception counters */
        l.movhi r11, 0
        l.ori r30, r0, 0xd /* put 0xd in r30, indicate it's databus test */
        /* Cause access error */
        /* Load word */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.lwz r6, 0(r5)
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Load half */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.lhz r6, 0(r5)
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Load byte */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.lbz r6, 0(r5)
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Store word */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.sw 0(r5), r6
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Store half */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.sh 0(r5), r6
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Store byte */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.sb 0(r5), r6
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        l.nop
        /* Delay slot tests */
        /* Load word */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 1f
        l.lwz r6, 0(r5) /* Data bus error in delay slot */
        l.nop
1:      l.addi r12, r12, 1
        /* Load half */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 2f
        l.lhz r6, 0(r5) /* Data bus error in delay slot */
        l.nop
2:      l.addi r12, r12, 1
        /* Load byte */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 3f
        l.lbz r6, 0(r5) /* Data bus error in delay slot */
        l.nop
3:      l.addi r12, r12, 1
        /* Store word */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 4f
        l.sw 0(r5), r6  /* Data bus error in delay slot */
        l.nop
4:      l.addi r12, r12, 1
        /* Store half */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 5f
        l.sh 0(r5), r6  /* Data bus error in delay slot */
        l.nop
5:      l.addi r12, r12, 1
        /* Store byte */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.j 6f
        l.sb 0(r5), r6  /* Data bus error in delay slot */
        l.nop
6:      l.addi r12, r12, 1
 
 
/* Check 1st and 2nd exception counters are equal */
        l.sfeq  r11,r12                 /* Should be equal */
        l.bf 7f
        l.nop
        l.or r3, r12, r12
        l.nop 2 /* Report expected exception count */
        l.or r3, r11, r11
        l.nop 2 /* Report actual exception count */
        l.nop 1
7:      l.nop
 
 
 
_ibus1:
        /* TODO: do this it with cache enabled/disabled */
        l.movhi r12, 0 /* Reset exception counters */
        l.movhi r11, 0
        l.movhi r30, 0x0 /* put 0x0 in r30,indicate it's instruction bus test*/
        /* Cause access error */
        l.movhi r5, 0xee00 /* Address to cause an error */
        l.jalr r5 /* Jump and link to bad address */
        l.nop
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
        /* Check 1st and 2nd exception counters are equal */
        l.sfeq  r11,r12                 /* Should be equal */
        l.bf 1f
        l.nop
        l.or r3, r12, r12
        l.nop 2 /* Report expected exception count */
        l.or r3, r11, r11
        l.nop 2 /* Report actual exception count */
        l.nop 1
1:      l.nop
        l.nop
 
 
        /* Data MMU exception - try case where we need to translate address as
           we l.rfe to it */
        // Check the DMMU is the in the design, otherwise don't compile in this
        // test.
#ifndef OR1200_NO_DMMU
        .extern lo_dmmu_en
_dmmu_except1:
        /* Call DMMU invalidate function */
        l.movhi r4, hi(_dmmu_invalidate)
        l.ori r4, r4, lo(_dmmu_invalidate)
        l.jalr r4
        l.ori r3, r0, 64 /* Put number of entries in r3 */
 
        l.movhi r5, hi(0x01000000)
        /* Write a word to the place where we'll translate to */
        l.movhi r7, hi(0xaabbccdd)
        l.ori r7, r7, lo(0xaabbccdd)
        l.sw 0(r5), r7 /* Shouldn't trigger MMU */
        l.sfne r18, r0
        l.bf _dmmu_test_error
        l.nop
        l.sfne r19, r0
        l.bf _dmmu_test_error
        l.nop
 
        /* Now enable DMMU */
        l.movhi r4, hi(lo_dmmu_en)
        l.ori r4, r4, lo(lo_dmmu_en)
        l.jalr r4
        l.nop
 
        /* Now start test. 0xc0000000 should go to 0x01000000 */
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
        /* Check value was OK */
        l.sfne r7, r8
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r18, 0x1 /* Check for lo mem mapping */
        l.bf _dmmu_test_error
        l.nop
        l.sfne r19, r0 /* hi-mem counter should still be 0 */
        l.bf _dmmu_test_error
        l.nop
 
        /* Test accesses to mapped area */
        l.movhi r6, hi(0xc0000000)
        l.lwz r8, 0(r6) /* Should cause DMMU miss, himem */
        /* Check value was OK */
        l.sfne r7, r8
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r18, 0x1 /* Check for lo mem mapping */
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r19, 0x1 /* hi-mem counter should still be 0 */
        l.bf _dmmu_test_error
        l.nop
 
        /* Now start test. 0xc0000000 should go to 0x01000000 */
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
        /* Check value was OK */
        l.sfne r7, r8
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r18, 0x2 /* Check for lo mem mapping increment */
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r19, 0x1 /* hi-mem counter should still be 1 */
        l.bf _dmmu_test_error
        l.nop
 
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
 
        l.sw 4(r6), r7 /* Should cause DMMU miss, himem */
        l.sfnei r18, 0x2 /* Check for lo mem mapping */
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r19, 0x2 /* hi-mem counter should be 2 */
        l.bf _dmmu_test_error
        l.nop
 
        l.lwz r8, 4(r5) /* Should cause DMMU miss, lomem */
        /* Check value was OK */
        l.sfne r7, r8
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r18, 0x3 /* Check for lo mem mapping increment */
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r19, 0x2 /* hi-mem counter should still be 2 */
        l.bf _dmmu_test_error
        l.nop
 
        /* Fast DMMU exceptions should follow */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 8(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 8(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0xc(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0xc(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x10(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x10(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x14(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x14(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x18(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x18(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x1c(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x1c(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x20(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x20(r5) /* Should cause DMMU miss, lomem */
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
        l.sw 0x24(r6), r7 /* Should cause DMMU miss, himem */
        l.lwz r8, 0x24(r5) /* Should cause DMMU miss, lomem */
        /* Should now be 11 lowmem DTLB misses and 10 for high memory space */
        l.sfne r7, r8
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r18, 0xb /* Check for lo mem mapping increment to 11 */
        l.bf _dmmu_test_error
        l.nop
        l.sfnei r19, 0xa /* hi-mem counter should be 10 */
        l.bf _dmmu_test_error
        l.nop
 
        l.j _dmmu_test_ok
        l.nop
 
 
_dmmu_test_error:
        l.movhi r3, hi(0xeeeeeeed)
        l.ori r3, r3, lo(0xeeeeeeed)
        l.nop 2
        l.nop 1
 
_dmmu_test_ok:
        l.nop
 
#endif // #ifndef OR1200_NO_DMMU
 
        /* End of tests - report and finish simulation */
        l.movhi r3,hi(0xdeaddead)
        l.ori   r3,r3,lo(0xdeaddead)
        l.nop   2
 
        l.movhi r3,hi(0x8000000d)
        l.ori   r3,r3,lo(0x8000000d)
        l.nop   2
 
        l.addi r3,r0,0
        l.jal   exit
        l.nop
 
 
        /* DMMU invalidate function */
        /* First parameter, r3, has number of DMMU entries (should be 64)*/
 
_dmmu_invalidate:
        /* Setup the Data MMU's TLBS */
        l.movhi r4, hi(SPR_DTLBMR_BASE(0))
        l.ori r4, r4, lo(SPR_DTLBMR_BASE(0))
 
        /* DTLB invalidate loop */
1:
        l.mtspr r4, r0, 0x0
        l.addi r4, r4, 0x1
        l.sfeq r3, r0
        l.bnf 1b
        l.addi r3, r3, -1
        l.jr r9
        l.nop
 

Line No.	Rev	Author	Line
1	349	julius	`/*`
2			`Exception test.`
3
4			`The following list outlines the tests performed`
5
6			`Execption test`
7			`- 0x100 reset - start addr after reset`
8			`- 0x200 bus error - unimplemented addr is accessed`
9			`- 0x300 data page fault - NOT tested here`
10			`- 0x400 instruction page fault - NOT tested here`
11			`- 0x500 tick timer - NOT tested here`
12			`- 0x600 alignment - write to unaligned addr`
13			`- 0x700 illegal instruction - use unimplemented inst. l.div`
14			`- 0x800 external interrupt - int triggered from wb slave`
15			`- 0x900 d-tlb miss - translation tests`
16			`- 0xA00 i-tlb miss - NOT tested here`
17			`- 0xB00 range - NOT tested here`
18			`- 0xC00 system call - NOT tested here`
19			`- 0xD00 floating point - NOT tested here`
20			`- 0xE00 trap - NOT tested here`
21			`- 0xF00 RESERVED`
22
23			`r11 - 1st exception counter incremented inside exception`
24			`r12 - 2nd exception counter incremented outside and rigth after`
25			`exception`
26			`... other register use to be documented...`
27
28			`Julius Baxter, julius@opencores.org`
29			`Tadej Markovic, tadej@opencores.org`
30
31			`*/`
32			`//////////////////////////////////////////////////////////////////////`
33			`//// ////`
34			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
35			`//// ////`
36			`//// This source file may be used and distributed without ////`
37			`//// restriction provided that this copyright statement is not ////`
38			`//// removed from the file and that any derivative work contains ////`
39			`//// the original copyright notice and the associated disclaimer. ////`
40			`//// ////`
41			`//// This source file is free software; you can redistribute it ////`
42			`//// and/or modify it under the terms of the GNU Lesser General ////`
43			`//// Public License as published by the Free Software Foundation; ////`
44			`//// either version 2.1 of the License, or (at your option) any ////`
45			`//// later version. ////`
46			`//// ////`
47			`//// This source is distributed in the hope that it will be ////`
48			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
49			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
50			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
51			`//// details. ////`
52			`//// ////`
53			`//// You should have received a copy of the GNU Lesser General ////`
54			`//// Public License along with this source; if not, download it ////`
55			`//// from http://www.opencores.org/lgpl.shtml ////`
56			`//// ////`
57			`//////////////////////////////////////////////////////////////////////`
58
59			`#include "spr-defs.h"`
60			`#include "board.h"`
61			`#include "or1200-defines.h"`
62
63			`/* =================================================== [ exceptions ] === */`
64			`.section .vectors, "ax"`
65
66
67			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
68			`.org 0x100`
69			`l.movhi r0, 0`
70			`/* Clear status register */`
71			`l.ori r1, r0, SPR_SR_SM`
72			`l.mtspr r0, r1, SPR_SR`
73			`/* Clear timer */`
74			`l.mtspr r0, r0, SPR_TTMR`
75			`/* Init the stack */`
76			`.global stack`
77			`l.movhi r1, hi(stack)`
78			`l.ori r1, r1, lo(stack)`
79			`l.addi r2, r0, -3`
80			`l.and r1, r1, r2`
81			`/* Jump to program initialisation code */`
82			`.global _start`
83			`l.movhi r4, hi(_start)`
84			`l.ori r4, r4, lo(_start)`
85			`l.jr r4`
86			`l.nop`
87
88
89			`/* ---[ 0x200: BUS error ]------------------------------------------------ */`
90			`.org 0x200`
91			`.global _bus_handler`
92			`_bus_handler:`
93			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPC */`
94			`l.nop 2`
95			`l.mfspr r3,r0,SPR_EEAR_BASE /* Get EEA */`
96			`l.nop 2`
97			`l.addi r11,r11,1 /* Increment 1st exception counter */`
98			`l.sfeqi r30, 0xd /* Is this a data bus test, if so return with l.rfe */`
99			`l.bf 1f`
100			`l.movhi r5, 0 /* r5 should be the one causing the error on dbus */`
101			`/* Instruction bus error test return */`
102			`l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */`
103			`l.ori r5, r5, lo(0x44004800)`
104			`l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */`
105			`l.movhi r5,0x1500 /* Put a "l.nop" instruction in r5 */`
106			`l.sw 0x4(r0),r5 /* Write l.nop instruction to RAM addr 0x4 */`
107			`l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */`
108			`l.mtspr r0,r0,SPR_EPCR_BASE /* RFE to 0x0, which is l.jr r9 */`
109			`1: l.rfe`
110
111			`/* ---[ 0x600: ALIGN error ]------------------------------------------------ */`
112			`.org 0x600`
113			`.global _align_handler`
114			`_align_handler:`
115			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPC */`
116			`l.nop 2`
117			`l.addi r11,r11,1 /* Increment 1st exception counter */`
118			`l.movhi r5,0 /* Clear the pointer register */`
119			`l.rfe`
120
121
122			`/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */`
123			`.org 0x700`
124			`.global _illinsn_handler`
125			`_illinsn_handler:`
126			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPC */`
127			`l.nop 2`
128			`l.addi r11,r11,1 /* Increment 1st exception counter */`
129			`/* Delay slot test needs this instruction "fixed" */`
130			`l.movhi r5,0x1500 /* Put a "l.nop" instruction in r5 */`
131			`l.sw 0x4(r0),r5 /* Write l.nop instruction to RAM addr 0x4 */`
132			`l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */`
133			`l.mtspr r0,r0,SPR_EPCR_BASE /* Jump to 0, which is l.jr r9 */`
134			`l.rfe`
135
136			`/* ---[ 0x900: DTLB exception ]--------------------------------------------- */`
137			`.org 0x900`
138			`.global _dtlb_handler`
139			`/* Exception handler - DMMU TLB miss */`
140			`/* Assume 64-entry TLB cache */`
141			`_dtlb_handler:`
142			`l.mfspr r20, r0, SPR_EEAR_BASE`
143			`/* Find the entry/set for this address */`
144			`l.srli r21, r20, 13 /* r21 = VPN, shift by size 8192 = 2*13 /`
145			`l.andi r22, r21, 0x3f /* 64 entries = 6 bit mask, r22 = set number */`
146			`/* If page is in the 0xc0000000 space we map to 16MB part of`
147			`memory, ie 0x0 => 0x01000000, otherwise 1-1 mapping */`
148			`l.movhi r23, hi(0xc0000000)`
149			`l.ori r23, r23, lo(0xc0000000)`
150			`l.srli r23, r23, 13 /* Get page address, shift by page size, 13 bits */`
151			`l.movhi r24, hi(0xff << 11) /* Mask for top byte of VPN */`
152			`l.ori r24, r24, lo(0xff << 11)`
153			`l.and r24, r24, r21 /* Mask in only top byte of VPN */`
154			`l.sfeq r23, r24 /* Decide if it's in our special mapped region or not*/`
155
156			`/* First, Setup value for DTLBM (match) reg, is same for both cases */`
157			`l.movhi r24, hi(SPR_ITLBMR_VPN) /* VPN mask into r24 */`
158			`l.ori r24, r24, lo(SPR_ITLBMR_VPN)`
159			`l.and r25, r20, r24 /* AND address with VPN mask */`
160			`l.ori r25, r25, SPR_DTLBMR_V /* OR in valid bit */`
161			`l.mtspr r22, r25, SPR_DTLBMR_BASE(0) /* Write to DTLBR register */`
162
163			`l.bf _highmem_map`
164			`l.nop`
165
166			`_lomem_map:`
167			`/* Do 1:1 mapping for this request */`
168			`/* Setup value for translate register */`
169			`l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */`
170			`l.ori r24, r24, lo(SPR_ITLBTR_PPN)`
171			`l.and r25, r20, r24 /* AND address with PPN mask */`
172			`l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */`
173			`l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */`
174			`l.j _dtlb_done`
175			`l.addi r18, r18, 1 /* Incremement low-mapping counter */`
176
177			`_highmem_map:`
178			`/* Do top byte, 0xc0->0x01, mapping for this request */`
179			`/* Setup value for translate register */`
180			`l.movhi r24, hi(SPR_ITLBTR_PPN) /* PPN mask into r24 */`
181			`l.ori r24, r24, lo(SPR_ITLBTR_PPN)`
182			`l.and r25, r20, r24 /* AND address with PPN mask */`
183			`l.movhi r26, hi(0xff000000) /* Top byte address mask */`
184			`l.or r25, r26, r25 /* Set top byte to 0xff */`
185			`l.xor r25, r26, r25 /* Now clear top byte with XOR */`
186			`l.movhi r26, hi(0x01000000) /* Top address byte */`
187			`l.or r25, r26, r25 /* Set top address byte */`
188			`l.ori r25, r25, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */`
189			`l.mtspr r22, r25, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */`
190			`l.addi r19, r19, 1 /* Incremement low-mapping counter */`
191
192			`_dtlb_done:`
193
194			`l.rfe`
195
196
197
198			`/* =================================================== [ text section ] === */`
199			`.section .text`
200
201			`/* =================================================== [ start ] === */`
202
203			`.global _start`
204			`_start:`
205
206			`/* Instruction cache enable */`
207			`/* Check if IC present and skip enabling otherwise */`
208			`l.mfspr r24,r0,SPR_UPR`
209			`l.andi r26,r24,SPR_UPR_ICP`
210			`l.sfeq r26,r0`
211			`l.bf .L8`
212			`l.nop`
213
214			`/* Disable IC */`
215			`l.mfspr r6,r0,SPR_SR`
216			`l.addi r5,r0,-1`
217			`l.xori r5,r5,SPR_SR_ICE`
218			`l.and r5,r6,r5`
219			`l.mtspr r0,r5,SPR_SR`
220
221			`/* Establish cache block size`
222			`If BS=0, 16;`
223			`If BS=1, 32;`
224			`r14 contain block size`
225			`*/`
226			`l.mfspr r24,r0,SPR_ICCFGR`
227			`l.andi r26,r24,SPR_ICCFGR_CBS`
228			`l.srli r28,r26,7`
229			`l.ori r30,r0,16`
230			`l.sll r14,r30,r28`
231
232			`/* Establish number of cache sets`
233			`r16 contains number of cache sets`
234			`r28 contains log(# of cache sets)`
235			`*/`
236			`l.andi r26,r24,SPR_ICCFGR_NCS`
237			`l.srli r28,r26,3`
238			`l.ori r30,r0,1`
239			`l.sll r16,r30,r28`
240
241			`/* Invalidate IC */`
242			`l.addi r6,r0,0`
243			`l.sll r5,r14,r28`
244
245			`.L7:`
246			`l.mtspr r0,r6,SPR_ICBIR`
247			`l.sfne r6,r5`
248			`l.bf .L7`
249			`l.add r6,r6,r14`
250
251			`/* Enable IC */`
252			`l.mfspr r6,r0,SPR_SR`
253			`l.ori r6,r6,SPR_SR_ICE`
254			`l.mtspr r0,r6,SPR_SR`
255			`l.nop`
256			`l.nop`
257			`l.nop`
258			`l.nop`
259			`l.nop`
260			`l.nop`
261			`l.nop`
262			`l.nop`
263
264			`.L8:`
265			`/* Data cache enable */`
266			`/* Check if DC present and skip enabling otherwise */`
267			`l.mfspr r24,r0,SPR_UPR`
268			`l.andi r26,r24,SPR_UPR_DCP`
269			`l.sfeq r26,r0`
270			`l.bf .L10`
271			`l.nop`
272			`/* Disable DC */`
273			`l.mfspr r6,r0,SPR_SR`
274			`l.addi r5,r0,-1`
275			`l.xori r5,r5,SPR_SR_DCE`
276			`l.and r5,r6,r5`
277			`l.mtspr r0,r5,SPR_SR`
278			`/* Establish cache block size`
279			`If BS=0, 16;`
280			`If BS=1, 32;`
281			`r14 contain block size`
282			`*/`
283			`l.mfspr r24,r0,SPR_DCCFGR`
284			`l.andi r26,r24,SPR_DCCFGR_CBS`
285			`l.srli r28,r26,7`
286			`l.ori r30,r0,16`
287			`l.sll r14,r30,r28`
288			`/* Establish number of cache sets`
289			`r16 contains number of cache sets`
290			`r28 contains log(# of cache sets)`
291			`*/`
292			`l.andi r26,r24,SPR_DCCFGR_NCS`
293			`l.srli r28,r26,3`
294			`l.ori r30,r0,1`
295			`l.sll r16,r30,r28`
296			`/* Invalidate DC */`
297			`l.addi r6,r0,0`
298			`l.sll r5,r14,r28`
299			`.L9:`
300			`l.mtspr r0,r6,SPR_DCBIR`
301			`l.sfne r6,r5`
302			`l.bf .L9`
303			`l.add r6,r6,r14`
304			`/* Enable DC */`
305			`l.mfspr r6,r0,SPR_SR`
306			`l.ori r6,r6,SPR_SR_DCE`
307			`l.mtspr r0,r6,SPR_SR`
308			`.L10:`
309			`// Kick off test`
310			`l.jal _main`
311			`l.nop`
312
313			`/* ========================================================= [ main ] === */`
314
315			`.global _main`
316			`.global _dmmu_invalidate`
317			`.global _dmmu_except1`
318
319			`_main:`
320			`l.nop`
321			`l.addi r3,r0,0`
322			`l.addi r5,r0,0`
323			`l.addi r11,r0,0 /* exception counter 1 */`
324			`l.addi r12,r0,0 /* exception counter 2 */`
325			`l.addi r13,r0,0`
326			`l.addi r18,r0,0 /* DMMU exception counter for low mem mapping */`
327			`l.addi r19,r0,0 /* DMMU exception counter for hi mem mapping */`
328			`l.sw 0x0(r0),r0 /* Initialize RAM */`
329			`l.sw 0x4(r0),r0 /* Initialize RAM */`
330			`l.sw 0x8(r0),r0 /* Initialize RAM */`
331			`l.sw 0xc(r0),r0 /* Initialize RAM */`
332			`l.sw 0x10(r0),r0 /* Initialize RAM */`
333			`l.sw 0x14(r0),r0 /* Initialize RAM */`
334			`l.sw 0x18(r0),r0 /* Initialize RAM */`
335			`l.sw 0x1c(r0),r0 /* Initialize RAM */`
336			`l.sw 0x20(r0),r0 /* Initialize RAM */`
337			`l.sw 0x24(r0),r0 /* Initialize RAM */`
338			`l.sw 0x28(r0),r0 /* Initialize RAM */`
339			`l.sw 0x2c(r0),r0 /* Initialize RAM */`
340			`l.sw 0x30(r0),r0 /* Initialize RAM */`
341			`l.sw 0x34(r0),r0 /* Initialize RAM */`
342			`l.sw 0x38(r0),r0 /* Initialize RAM */`
343			`l.sw 0x3c(r0),r0 /* Initialize RAM */`
344			`l.sw 0x40(r0),r0 /* Initialize RAM */`
345			`l.sw 0x44(r0),r0 /* Initialize RAM */`
346			`l.sw 0x48(r0),r0 /* Initialize RAM */`
347			`l.sw 0x4c(r0),r0 /* Initialize RAM */`
348			`l.j _align1`
349			`//l.j _dmmu_except1`
350			`l.nop`
351
352
353			`/* Exceptions followed by NOPs */`
354
355			`/* SW alignment exception */`
356			`_align1:`
357			`l.movhi r11,0`
358			`l.nop`
359			`/* Test l.sh */`
360			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
361			`l.sh 0x0(r5),r0`
362			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
363			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
364			`l.sh 0x0(r5),r0`
365			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
366			`/* Test l.lhz */`
367			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
368			`l.lhz r3,0x0(r5)`
369			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
370			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
371			`l.lhz r3,0x0(r5)`
372			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
373			`/* Test l.lhs */`
374			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
375			`l.lhs r3,0x0(r5)`
376			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
377			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
378			`l.lhs r3,0x0(r5)`
379			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
380			`/* Test l.sw */`
381			`l.ori r5,r0,0x1 /* Word access, offset 1 */`
382			`l.sw 0x0(r5), r0`
383			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
384			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
385			`l.sw 0x0(r5), r0`
386			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
387			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
388			`l.sw 0x0(r5), r0`
389			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
390			`/* Test l.lwz */`
391			`l.ori r5,r0,0x1 /* Word access, offset 1 */`
392			`l.lwz r3,0x0(r5)`
393			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
394			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
395			`l.lwz r3,0x0(r5)`
396			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
397			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
398			`l.lwz r3,0x0(r5)`
399			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
400			`#if OR1200_HAS_LWS==1`
401			`/* Test l.lws */`
402			`l.ori r5,r0,0x1 /* Word access, offset 1 */`
403			`l.lws r3,0x0(r5)`
404			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
405			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
406			`l.lws r3,0x0(r5)`
407			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
408			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
409			`l.lws r3,0x0(r5)`
410			`l.addi r12,r12,1 /* Increment 2nd exception counter */`
411			`l.nop`
412			`#endif`
413			`/* Now test them in delay slots */`
414
415			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
416			`l.j 1f`
417			`l.sh 0x0(r5),r0`
418			`l.nop`
419			`1: l.addi r12,r12,1 /* Increment 2nd exception counter */`
420			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
421			`l.j 2f`
422			`l.sh 0x0(r5),r0`
423			`l.nop`
424			`2: l.addi r12,r12,1 /* Increment 2nd exception counter */`
425
426			`/* Test l.lhz */`
427			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
428			`l.j 3f`
429			`l.lhz r3,0x0(r5)`
430			`l.nop`
431			`3: l.addi r12,r12,1 /* Increment 2nd exception counter */`
432			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
433			`l.j 4f`
434			`l.lhz r3,0x0(r5)`
435			`l.nop`
436			`4: l.addi r12,r12,1 /* Increment 2nd exception counter */`
437
438			`/* Test l.lhs */`
439			`l.ori r5,r0,0x1 /* Half-word access, offset 1 */`
440			`l.j 5f`
441			`l.lhs r3,0x0(r5)`
442			`l.nop`
443			`5: l.addi r12,r12,1 /* Increment 2nd exception counter */`
444			`l.ori r5,r0,0x3 /* Half-word access, offset 3 */`
445			`l.j 6f`
446			`l.lhs r3,0x0(r5)`
447			`l.nop`
448			`6: l.addi r12,r12,1 /* Increment 2nd exception counter */`
449
450			`/* Test l.sw */`
451	412	julius	`l.ori r5,r0,0x1 /* Word access, offset 1 */`
452			`l.j 7f`
453			`l.sw 0x0(r5), r0`
454	349	julius	`l.nop`
455	412	julius	`7: l.addi r12,r12,1 /* Increment 2nd exception counter */`
456			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
457			`l.j 8f`
458			`l.sw 0x0(r5), r0`
459	349	julius	`l.nop`
460	412	julius	`8: l.addi r12,r12,1 /* Increment 2nd exception counter */`
461			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
462			`l.j 9f`
463			`l.sh 0x0(r5), r0`
464	349	julius	`l.nop`
465	412	julius	`9: l.addi r12,r12,1 /* Increment 2nd exception counter */`
466	349	julius
467			`/* Test l.lwz */`
468	412	julius	`l.ori r5,r0,0x1 /* Word access, offset 1 */`
469			`l.j 10f`
470			`l.lwz r3,0x0(r5)`
471	349	julius	`l.nop`
472	412	julius	`10: l.addi r12,r12,1 /* Increment 2nd exception counter */`
473			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
474			`l.j 11f`
475			`l.lwz r3,0x0(r5)`
476	349	julius	`l.nop`
477	412	julius	`11: l.addi r12,r12,1 /* Increment 2nd exception counter */`
478			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
479			`l.j 12f`
480			`l.lwz r3,0x0(r5)`
481	349	julius	`l.nop`
482	412	julius	`12: l.addi r12,r12,1 /* Increment 2nd exception counter */`
483	349	julius	`#if OR1200_HAS_LWS==1`
484			`/* Test l.lws */`
485	412	julius	`l.ori r5,r0,0x1 /* Word access, offset 1 */`
486			`l.j 13f`
487			`l.lws r3,0x0(r5)`
488	349	julius	`l.nop`
489	412	julius	`13: l.addi r12,r12,1 /* Increment 2nd exception counter */`
490			`l.ori r5,r0,0x2 /* Word access, offset 2 */`
491			`l.j 14f`
492			`l.lws r3,0x0(r5)`
493	349	julius	`l.nop`
494	412	julius	`14: l.addi r12,r12,1 /* Increment 2nd exception counter */`
495			`l.ori r5,r0,0x3 /* Word access, offset 3 */`
496			`l.j 15f`
497			`l.lws r3,0x0(r5)`
498	349	julius	`l.nop`
499	412	julius	`15: l.addi r12,r12,1 /* Increment 2nd exception counter */`
500	349	julius

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