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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-except.S] - Blame information for rev 545

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Line No. Rev Author Line
1 349 julius
/*
2
        Exception test.
3
 
4
        The following list outlines the tests performed
5
 
6
        Execption test
7
        - 0x100 reset                        - start addr after reset
8
        - 0x200 bus error                    - unimplemented addr is accessed
9
        - 0x300 data page fault              - NOT tested here
10
        - 0x400 instruction page fault       - NOT tested here
11
        - 0x500 tick timer                   - NOT tested here
12
        - 0x600 alignment                    - write to unaligned addr
13
        - 0x700 illegal instruction          - use unimplemented inst. l.div
14
        - 0x800 external interrupt           - int triggered from wb slave
15
        - 0x900 d-tlb miss                   - translation tests
16
        - 0xA00 i-tlb miss                   - NOT tested here
17
        - 0xB00 range                        - NOT tested here
18
        - 0xC00 system call                  - NOT tested here
19
        - 0xD00 floating point               - NOT tested here
20
        - 0xE00 trap                         - NOT tested here
21
        - 0xF00 RESERVED
22
 
23
        r11 - 1st exception counter incremented inside exception
24
        r12 - 2nd exception counter incremented outside and rigth after
25
              exception
26
        ... other register use to be documented...
27
 
28
        Julius Baxter, julius@opencores.org
29
        Tadej Markovic, tadej@opencores.org
30
 
31
*/
32
//////////////////////////////////////////////////////////////////////
33
////                                                              ////
34
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
35
////                                                              ////
36
//// This source file may be used and distributed without         ////
37
//// restriction provided that this copyright statement is not    ////
38
//// removed from the file and that any derivative work contains  ////
39
//// the original copyright notice and the associated disclaimer. ////
40
////                                                              ////
41
//// This source file is free software; you can redistribute it   ////
42
//// and/or modify it under the terms of the GNU Lesser General   ////
43
//// Public License as published by the Free Software Foundation; ////
44
//// either version 2.1 of the License, or (at your option) any   ////
45
//// later version.                                               ////
46
////                                                              ////
47
//// This source is distributed in the hope that it will be       ////
48
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
49
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
50
//// PURPOSE.  See the GNU Lesser General Public License for more ////
51
//// details.                                                     ////
52
////                                                              ////
53
//// You should have received a copy of the GNU Lesser General    ////
54
//// Public License along with this source; if not, download it   ////
55
//// from http://www.opencores.org/lgpl.shtml                     ////
56
////                                                              ////
57
//////////////////////////////////////////////////////////////////////
58
 
59
#include "spr-defs.h"
60
#include "board.h"
61
#include "or1200-defines.h"
62
 
63
/* =================================================== [ exceptions ] === */
64
        .section .vectors, "ax"
65
 
66
 
67
/* ---[ 0x100: RESET exception ]----------------------------------------- */
68
        .org 0x100
69
        l.movhi r0, 0
70
        /* Clear status register */
71
        l.ori   r1, r0, SPR_SR_SM
72
        l.mtspr r0, r1, SPR_SR
73
        /* Clear timer  */
74
        l.mtspr r0, r0, SPR_TTMR
75
        /* Init the stack */
76
        .global stack
77
        l.movhi r1, hi(stack)
78
        l.ori   r1, r1, lo(stack)
79
        l.addi  r2, r0, -3
80
        l.and   r1, r1, r2
81
        /* Jump to program initialisation code */
82
        .global _start
83
        l.movhi r4, hi(_start)
84
        l.ori   r4, r4, lo(_start)
85
        l.jr    r4
86
        l.nop
87
 
88
 
89
/* ---[ 0x200: BUS error ]------------------------------------------------ */
90
        .org 0x200
91
        .global _bus_handler
92
_bus_handler:
93
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
94
        l.nop   2
95
        l.mfspr r3,r0,SPR_EEAR_BASE     /* Get EEA */
96
        l.nop   2
97
        l.addi  r11,r11,1               /* Increment 1st exception counter */
98 530 julius
        l.sfeqi r2, 0xd /* Is this a data bus test, if so return with l.rfe */
99 349 julius
        l.bf 1f
100
        l.movhi r5, 0    /* r5 should be the one causing the error on dbus */
101
        /* Instruction bus error test return */
102
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
103
        l.ori r5, r5, lo(0x44004800)
104
        l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
105
        l.movhi r5,0x1500       /* Put a "l.nop"  instruction in r5 */
106
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
107
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
108
        l.mtspr r0,r0,SPR_EPCR_BASE     /* RFE to 0x0, which is l.jr r9 */
109
1:      l.rfe
110
 
111
/* ---[ 0x600: ALIGN error ]------------------------------------------------ */
112
        .org 0x600
113
        .global _align_handler
114
_align_handler:
115
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
116
        l.nop   2
117
        l.addi  r11,r11,1               /* Increment 1st exception counter */
118
        l.movhi r5,0                    /* Clear the pointer register */
119
        l.rfe
120
 
121
 
122
/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
123
        .org 0x700
124
        .global _illinsn_handler
125
_illinsn_handler:
126
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPC */
127
        l.nop   2
128
        l.addi  r11,r11,1               /* Increment 1st exception counter */
129
        /* Delay slot test needs this instruction "fixed" */
130
        l.movhi r5,0x1500               /* Put a "l.nop"  instruction in r5 */
131
        l.sw    0x4(r0),r5      /* Write l.nop instruction to RAM addr 0x4 */
132
        l.mtspr r0,r0,SPR_ICBIR         /* Invalidate line 0 of cache */
133
        l.mtspr r0,r0,SPR_EPCR_BASE     /* Jump to 0, which is l.jr r9 */
134
        l.rfe
135
 
136
/* ---[ 0x900: DTLB exception ]--------------------------------------------- */
137
        .org 0x900
138
        .global _dtlb_handler
139
/* Exception handler - DMMU TLB miss */
140
/* Assume 64-entry TLB cache */
141 530 julius
_dtlb_handler:
142
        l.sw    -4(r1),r4
143
        l.sw    -8(r1),r5
144
        l.sw    -12(r1),r6
145
        l.sw    -16(r1),r7
146
        l.sw    -20(r1),r8
147
        l.mfspr r2, r0, SPR_EEAR_BASE
148 349 julius
        /* Find the entry/set for this address */
149 530 julius
        l.srli r13, r2, 13 /* r13 = VPN, shift by size 8192 = 2**13 */
150
        l.andi r4, r13, 0x3f /* 64 entries = 6 bit mask, r4 = set number */
151 349 julius
        /* If page is in the 0xc0000000 space we map to 16MB part of
152
        memory, ie 0x0 => 0x01000000, otherwise 1-1 mapping */
153 530 julius
        l.movhi r5, hi(0xc0000000)
154
        l.ori r5, r5, lo(0xc0000000)
155
        l.srli r5, r5, 13 /* Get page address, shift by page size, 13 bits */
156
        l.movhi r6, hi(0xff << 11) /* Mask for top byte of VPN */
157
        l.ori r6, r6, lo(0xff << 11)
158
        l.and r6, r6, r13 /* Mask in only top byte of VPN */
159
        l.sfeq r5, r6 /* Decide if it's in our special mapped region or not*/
160 349 julius
 
161
        /* First, Setup value for DTLBM (match) reg, is same for both cases */
162 530 julius
        l.movhi r6, hi(SPR_ITLBMR_VPN) /* VPN mask into r6 */
163
        l.ori r6, r6, lo(SPR_ITLBMR_VPN)
164
        l.and r7, r2, r6 /* AND address with VPN mask */
165
        l.ori r7, r7, SPR_DTLBMR_V /* OR in valid bit */
166
        l.mtspr r4, r7, SPR_DTLBMR_BASE(0) /* Write to DTLBR register */
167 349 julius
 
168
        l.bf _highmem_map
169
        l.nop
170
 
171
_lomem_map:
172
        /* Do 1:1 mapping for this request */
173
        /* Setup value for translate register */
174 530 julius
        l.movhi r6, hi(SPR_ITLBTR_PPN) /* PPN mask into r6 */
175
        l.ori r6, r6, lo(SPR_ITLBTR_PPN)
176
        l.and r7, r2, r6 /* AND address with PPN mask */
177
        l.ori r7, r7, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
178
        l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
179 349 julius
        l.j _dtlb_done
180 530 julius
        l.addi r14, r14, 1 /* Incremement low-mapping counter */
181 349 julius
 
182
_highmem_map:
183
        /* Do top byte, 0xc0->0x01, mapping for this request */
184
        /* Setup value for translate register */
185 530 julius
        l.movhi r6, hi(SPR_ITLBTR_PPN) /* PPN mask into r6 */
186
        l.ori r6, r6, lo(SPR_ITLBTR_PPN)
187
        l.and r7, r2, r6 /* AND address with PPN mask */
188
        l.movhi r8, hi(0xff000000) /* Top byte address mask */
189
        l.or r7, r8, r7 /* Set top byte to 0xff */
190
        l.xor r7, r8, r7 /* Now clear top byte with XOR */
191
        l.movhi r8, hi(0x01000000) /* Top address byte */
192
        l.or r7, r8, r7 /* Set top address byte */
193
        l.ori r7, r7, DTLB_PR_NOLIMIT /* Set all execute enables, no lims. */
194
        l.mtspr r4, r7, SPR_DTLBTR_BASE(0) /* Write to DTLTR register */
195
        l.addi r15, r15, 1 /* Incremement low-mapping counter */
196 349 julius
 
197
_dtlb_done:
198 530 julius
        l.lwz   r4,-4(r1)
199
        l.lwz   r5,-8(r1)
200
        l.lwz   r6,-12(r1)
201
        l.lwz   r7,-16(r1)
202
        l.lwz   r8,-20(r1)
203 349 julius
        l.rfe
204
 
205
 
206
 
207
/* =================================================== [ text section ] === */
208
        .section  .text
209
 
210
/* =================================================== [ start ] === */
211
 
212
        .global _start
213
_start:
214 530 julius
        l.jal   _cache_init
215 349 julius
        l.nop
216
        // Kick off test
217
        l.jal   _main
218
        l.nop
219
 
220
/* ========================================================= [ main ] === */
221
 
222
        .global _main
223
        .global _dmmu_invalidate
224
        .global _dmmu_except1
225
 
226
_main:
227
        l.nop
228
        l.addi  r3,r0,0
229
        l.addi  r5,r0,0
230
        l.addi  r11,r0,0 /* exception counter 1 */
231
        l.addi  r12,r0,0 /* exception counter 2 */
232
        l.addi  r13,r0,0
233 530 julius
        l.addi  r14,r0,0 /* DMMU exception counter for low mem mapping */
234
        l.addi  r15,r0,0 /* DMMU exception counter for hi mem mapping */
235 349 julius
        l.sw    0x0(r0),r0      /* Initialize RAM */
236
        l.sw    0x4(r0),r0      /* Initialize RAM */
237
        l.sw    0x8(r0),r0      /* Initialize RAM */
238
        l.sw    0xc(r0),r0      /* Initialize RAM */
239
        l.sw    0x10(r0),r0     /* Initialize RAM */
240
        l.sw    0x14(r0),r0     /* Initialize RAM */
241
        l.sw    0x18(r0),r0     /* Initialize RAM */
242
        l.sw    0x1c(r0),r0     /* Initialize RAM */
243
        l.sw    0x20(r0),r0     /* Initialize RAM */
244
        l.sw    0x24(r0),r0     /* Initialize RAM */
245
        l.sw    0x28(r0),r0     /* Initialize RAM */
246
        l.sw    0x2c(r0),r0     /* Initialize RAM */
247
        l.sw    0x30(r0),r0     /* Initialize RAM */
248
        l.sw    0x34(r0),r0     /* Initialize RAM */
249
        l.sw    0x38(r0),r0     /* Initialize RAM */
250
        l.sw    0x3c(r0),r0     /* Initialize RAM */
251
        l.sw    0x40(r0),r0     /* Initialize RAM */
252
        l.sw    0x44(r0),r0     /* Initialize RAM */
253
        l.sw    0x48(r0),r0     /* Initialize RAM */
254
        l.sw    0x4c(r0),r0     /* Initialize RAM */
255
        l.j     _align1
256
        //l.j _dmmu_except1
257
        l.nop
258
 
259
 
260
        /* Exceptions followed by NOPs */
261
 
262
        /* SW alignment exception */
263
_align1:
264
        l.movhi r11,0
265
        l.nop
266
        /* Test l.sh */
267
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
268
        l.sh 0x0(r5),r0
269
        l.addi r12,r12,1 /* Increment 2nd exception counter */
270
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
271
        l.sh 0x0(r5),r0
272
        l.addi r12,r12,1 /* Increment 2nd exception counter */
273
        /* Test l.lhz */
274
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
275
        l.lhz r3,0x0(r5)
276
        l.addi r12,r12,1 /* Increment 2nd exception counter */
277
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
278
        l.lhz r3,0x0(r5)
279
        l.addi r12,r12,1 /* Increment 2nd exception counter */
280
        /* Test l.lhs */
281
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
282
        l.lhs r3,0x0(r5)
283
        l.addi r12,r12,1 /* Increment 2nd exception counter */
284
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
285
        l.lhs r3,0x0(r5)
286
        l.addi r12,r12,1 /* Increment 2nd exception counter */
287
        /* Test l.sw */
288
        l.ori r5,r0,0x1 /* Word access, offset 1 */
289
        l.sw 0x0(r5), r0
290
        l.addi r12,r12,1 /* Increment 2nd exception counter */
291
        l.ori r5,r0,0x2 /* Word access, offset 2 */
292
        l.sw 0x0(r5), r0
293
        l.addi r12,r12,1 /* Increment 2nd exception counter */
294
        l.ori r5,r0,0x3 /* Word access, offset 3 */
295
        l.sw 0x0(r5), r0
296
        l.addi r12,r12,1 /* Increment 2nd exception counter */
297
        /* Test l.lwz */
298
        l.ori r5,r0,0x1 /* Word access, offset 1 */
299
        l.lwz r3,0x0(r5)
300
        l.addi r12,r12,1 /* Increment 2nd exception counter */
301
        l.ori r5,r0,0x2 /* Word access, offset 2 */
302
        l.lwz r3,0x0(r5)
303
        l.addi r12,r12,1 /* Increment 2nd exception counter */
304
        l.ori r5,r0,0x3 /* Word access, offset 3 */
305
        l.lwz r3,0x0(r5)
306
        l.addi r12,r12,1 /* Increment 2nd exception counter */
307
#if OR1200_HAS_LWS==1
308
        /* Test l.lws */
309
        l.ori r5,r0,0x1 /* Word access, offset 1 */
310
        l.lws r3,0x0(r5)
311
        l.addi r12,r12,1 /* Increment 2nd exception counter */
312
        l.ori r5,r0,0x2 /* Word access, offset 2 */
313
        l.lws r3,0x0(r5)
314
        l.addi r12,r12,1 /* Increment 2nd exception counter */
315
        l.ori r5,r0,0x3 /* Word access, offset 3 */
316
        l.lws r3,0x0(r5)
317
        l.addi r12,r12,1 /* Increment 2nd exception counter */
318
        l.nop
319
#endif
320
        /* Now test them in delay slots */
321
 
322
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
323
        l.j 1f
324
        l.sh 0x0(r5),r0
325
        l.nop
326
1:      l.addi r12,r12,1 /* Increment 2nd exception counter */
327
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
328
        l.j 2f
329
        l.sh 0x0(r5),r0
330
        l.nop
331
2:      l.addi r12,r12,1 /* Increment 2nd exception counter */
332
 
333
        /* Test l.lhz */
334
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
335
        l.j 3f
336
        l.lhz r3,0x0(r5)
337
        l.nop
338
3:      l.addi r12,r12,1 /* Increment 2nd exception counter */
339
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
340
        l.j 4f
341
        l.lhz r3,0x0(r5)
342
        l.nop
343
4:      l.addi r12,r12,1 /* Increment 2nd exception counter */
344
 
345
        /* Test l.lhs */
346
        l.ori r5,r0,0x1 /* Half-word access, offset 1 */
347
        l.j 5f
348
        l.lhs r3,0x0(r5)
349
        l.nop
350
5:      l.addi r12,r12,1 /* Increment 2nd exception counter */
351
        l.ori r5,r0,0x3 /* Half-word access, offset 3 */
352
        l.j 6f
353
        l.lhs r3,0x0(r5)
354
        l.nop
355
6:      l.addi r12,r12,1 /* Increment 2nd exception counter */
356
 
357
        /* Test l.sw */
358 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
359
        l.j     7f
360
        l.sw    0x0(r5), r0
361 349 julius
        l.nop
362 412 julius
7:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
363
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
364
        l.j     8f
365
        l.sw    0x0(r5), r0
366 349 julius
        l.nop
367 412 julius
8:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
368
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
369
        l.j     9f
370
        l.sh    0x0(r5), r0
371 349 julius
        l.nop
372 412 julius
9:      l.addi  r12,r12,1 /* Increment 2nd exception counter */
373 349 julius
 
374
        /* Test l.lwz */
375 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
376
        l.j     10f
377
        l.lwz   r3,0x0(r5)
378 349 julius
        l.nop
379 412 julius
10:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
380
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
381
        l.j     11f
382
        l.lwz   r3,0x0(r5)
383 349 julius
        l.nop
384 412 julius
11:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
385
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
386
        l.j     12f
387
        l.lwz   r3,0x0(r5)
388 349 julius
        l.nop
389 412 julius
12:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
390 349 julius
#if OR1200_HAS_LWS==1
391
        /* Test l.lws */
392 412 julius
        l.ori   r5,r0,0x1 /* Word access, offset 1 */
393
        l.j     13f
394
        l.lws   r3,0x0(r5)
395 349 julius
        l.nop
396 412 julius
13:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
397
        l.ori   r5,r0,0x2 /* Word access, offset 2 */
398
        l.j     14f
399
        l.lws   r3,0x0(r5)
400 349 julius
        l.nop
401 412 julius
14:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
402
        l.ori   r5,r0,0x3 /* Word access, offset 3 */
403
        l.j     15f
404
        l.lws   r3,0x0(r5)
405 349 julius
        l.nop
406 412 julius
15:     l.addi  r12,r12,1 /* Increment 2nd exception counter */
407 349 julius
 
408
#endif
409
        /* Check 1st and 2nd exception counters are equal */
410
        l.sfeq  r11,r12                 /* Should be equal */
411
        l.bf    17f
412
        l.nop
413
        l.nop   1
414
17:     l.nop   2
415
        l.nop
416
 
417
        /* Illegal instruction exception */
418
_illegal1:
419
        l.nop
420
        l.nop
421
        l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
422 412 julius
        l.ori   r5, r5, lo(0x44004800)
423 426 julius
        l.sw    0x0(r0), r5     /* Write "l.j r9" to address 0x0 in RAM */
424
        l.movhi r5, 0xee00      /* Put an illegal instruction in r5 */
425
        l.sw    0x4(r0), r5     /* Write illegal instruction to RAM addr 0x4 */
426
        l.movhi r5, 0x1500      /* l.nop after illegal instruction */
427
        l.sw    0x8(r0), r5     /* Write nop to RAM addr 0x8 */
428 349 julius
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
429 426 julius
        /* Jump to 0x4 - illegal opcode instruction */
430 412 julius
        l.ori   r6, r0, 0x4
431 426 julius
        l.jalr  r6              /* Jump to address 0x4, land on illegal insn */
432
        l.addi  r12,r12,1       /* Increment 2nd exception counter */
433
        l.nop                   /* Should return here */
434 349 julius
        l.nop
435
 
436
        /* Test in delay slot */
437
 
438 426 julius
        l.movhi r5, 0xee00      /* Put an illegal instruction in r5 */
439
        l.sw    0x4(r0), r5     /* Write illegal instruction to RAM addr 0x4 */
440 412 julius
        l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
441
        l.jalr  r0 /* Jump to address 0, will be a jump back but with an illegal
442 349 julius
                     dslot instruction which will befixed by handler */
443 426 julius
        l.addi  r12,r12,1       /* Increment 2nd exception counter */
444
        l.nop                   /* Should return here */
445 349 julius
 
446
        /* Check 1st and 2nd exception counters are equal */
447 426 julius
        l.sfeq  r11,r12         /* Should be equal */
448 412 julius
        l.bf    1f
449 349 julius
        l.nop
450 412 julius
        l.or    r3, r12, r12
451 426 julius
        l.nop   2               /* Report expected exception count */
452 412 julius
        l.or    r3, r11, r11
453 426 julius
        l.nop   2               /* Report actual exception count */
454 412 julius
        l.nop   1
455 349 julius
1:      l.nop
456
        l.nop
457
 
458
 
459
_dbus1:
460
        l.nop
461
        l.movhi r12, 0 /* Reset exception counters */
462
        l.movhi r11, 0
463 530 julius
        l.ori r2, r0, 0xd /* put 0xd in r2, indicate it's databus test */
464 349 julius
        /* Cause access error */
465
        /* Load word */
466
        l.movhi r5, 0xee00 /* Address to cause an error */
467
        l.lwz r6, 0(r5)
468
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
469
        /* Load half */
470
        l.movhi r5, 0xee00 /* Address to cause an error */
471
        l.lhz r6, 0(r5)
472
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
473
        /* Load byte */
474
        l.movhi r5, 0xee00 /* Address to cause an error */
475
        l.lbz r6, 0(r5)
476
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
477
        /* Store word */
478
        l.movhi r5, 0xee00 /* Address to cause an error */
479
        l.sw 0(r5), r6
480
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
481
        /* Store half */
482
        l.movhi r5, 0xee00 /* Address to cause an error */
483
        l.sh 0(r5), r6
484
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
485
        /* Store byte */
486
        l.movhi r5, 0xee00 /* Address to cause an error */
487
        l.sb 0(r5), r6
488
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
489
        l.nop
490
        /* Delay slot tests */
491
        /* Load word */
492
        l.movhi r5, 0xee00 /* Address to cause an error */
493
        l.j 1f
494
        l.lwz r6, 0(r5) /* Data bus error in delay slot */
495
        l.nop
496
1:      l.addi r12, r12, 1
497
        /* Load half */
498
        l.movhi r5, 0xee00 /* Address to cause an error */
499
        l.j 2f
500
        l.lhz r6, 0(r5) /* Data bus error in delay slot */
501
        l.nop
502
2:      l.addi r12, r12, 1
503
        /* Load byte */
504
        l.movhi r5, 0xee00 /* Address to cause an error */
505
        l.j 3f
506
        l.lbz r6, 0(r5) /* Data bus error in delay slot */
507
        l.nop
508
3:      l.addi r12, r12, 1
509
        /* Store word */
510
        l.movhi r5, 0xee00 /* Address to cause an error */
511
        l.j 4f
512
        l.sw 0(r5), r6  /* Data bus error in delay slot */
513
        l.nop
514
4:      l.addi r12, r12, 1
515
        /* Store half */
516
        l.movhi r5, 0xee00 /* Address to cause an error */
517
        l.j 5f
518
        l.sh 0(r5), r6  /* Data bus error in delay slot */
519
        l.nop
520
5:      l.addi r12, r12, 1
521
        /* Store byte */
522
        l.movhi r5, 0xee00 /* Address to cause an error */
523
        l.j 6f
524
        l.sb 0(r5), r6  /* Data bus error in delay slot */
525
        l.nop
526
6:      l.addi r12, r12, 1
527
 
528
 
529
/* Check 1st and 2nd exception counters are equal */
530
        l.sfeq  r11,r12                 /* Should be equal */
531
        l.bf 7f
532
        l.nop
533
        l.or r3, r12, r12
534
        l.nop 2 /* Report expected exception count */
535
        l.or r3, r11, r11
536
        l.nop 2 /* Report actual exception count */
537
        l.nop 1
538
7:      l.nop
539
 
540
 
541
 
542
_ibus1:
543
        /* TODO: do this it with cache enabled/disabled */
544
        l.movhi r12, 0 /* Reset exception counters */
545
        l.movhi r11, 0
546 530 julius
        l.movhi r2, 0x0 /* put 0x0 in r2,indicate it's instruction bus test*/
547 349 julius
        /* Cause access error */
548
        l.movhi r5, 0xee00 /* Address to cause an error */
549
        l.jalr r5 /* Jump and link to bad address */
550
        l.nop
551
        l.addi r12, r12, 1 /* Incremement secondary exception counter */
552
        /* Check 1st and 2nd exception counters are equal */
553
        l.sfeq  r11,r12                 /* Should be equal */
554
        l.bf 1f
555
        l.nop
556
        l.or r3, r12, r12
557
        l.nop 2 /* Report expected exception count */
558
        l.or r3, r11, r11
559
        l.nop 2 /* Report actual exception count */
560
        l.nop 1
561
1:      l.nop
562
        l.nop
563
 
564
 
565
        /* Data MMU exception - try case where we need to translate address as
566
           we l.rfe to it */
567
        // Check the DMMU is the in the design, otherwise don't compile in this
568
        // test.
569
#ifndef OR1200_NO_DMMU
570 373 julius
        .extern lo_dmmu_en
571 349 julius
_dmmu_except1:
572
        /* Call DMMU invalidate function */
573
        l.movhi r4, hi(_dmmu_invalidate)
574
        l.ori r4, r4, lo(_dmmu_invalidate)
575
        l.jalr r4
576
        l.ori r3, r0, 64 /* Put number of entries in r3 */
577
 
578
        l.movhi r5, hi(0x01000000)
579
        /* Write a word to the place where we'll translate to */
580
        l.movhi r7, hi(0xaabbccdd)
581
        l.ori r7, r7, lo(0xaabbccdd)
582
        l.sw 0(r5), r7 /* Shouldn't trigger MMU */
583 530 julius
        l.sfne r14, r0
584 349 julius
        l.bf _dmmu_test_error
585
        l.nop
586 530 julius
        l.sfne r15, r0
587 349 julius
        l.bf _dmmu_test_error
588
        l.nop
589
 
590
        /* Now enable DMMU */
591 373 julius
        l.movhi r4, hi(lo_dmmu_en)
592
        l.ori r4, r4, lo(lo_dmmu_en)
593 349 julius
        l.jalr r4
594
        l.nop
595
 
596
        /* Now start test. 0xc0000000 should go to 0x01000000 */
597
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
598
        /* Check value was OK */
599
        l.sfne r7, r8
600
        l.bf _dmmu_test_error
601
        l.nop
602 530 julius
        l.sfnei r14, 0x1 /* Check for lo mem mapping */
603 349 julius
        l.bf _dmmu_test_error
604
        l.nop
605 530 julius
        l.sfne r15, r0 /* hi-mem counter should still be 0 */
606 349 julius
        l.bf _dmmu_test_error
607
        l.nop
608
 
609
        /* Test accesses to mapped area */
610
        l.movhi r6, hi(0xc0000000)
611
        l.lwz r8, 0(r6) /* Should cause DMMU miss, himem */
612
        /* Check value was OK */
613
        l.sfne r7, r8
614
        l.bf _dmmu_test_error
615
        l.nop
616 530 julius
        l.sfnei r14, 0x1 /* Check for lo mem mapping */
617 349 julius
        l.bf _dmmu_test_error
618
        l.nop
619 530 julius
        l.sfnei r15, 0x1 /* hi-mem counter should still be 0 */
620 349 julius
        l.bf _dmmu_test_error
621
        l.nop
622
 
623
        /* Now start test. 0xc0000000 should go to 0x01000000 */
624
        l.lwz r8, 0(r5) /* Should cause DMMU miss, lomem */
625
        /* Check value was OK */
626
        l.sfne r7, r8
627
        l.bf _dmmu_test_error
628
        l.nop
629 530 julius
        l.sfnei r14, 0x2 /* Check for lo mem mapping increment */
630 349 julius
        l.bf _dmmu_test_error
631
        l.nop
632 530 julius
        l.sfnei r15, 0x1 /* hi-mem counter should still be 1 */
633 349 julius
        l.bf _dmmu_test_error
634
        l.nop
635
 
636
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
637
 
638
        l.sw 4(r6), r7 /* Should cause DMMU miss, himem */
639 530 julius
        l.sfnei r14, 0x2 /* Check for lo mem mapping */
640 349 julius
        l.bf _dmmu_test_error
641
        l.nop
642 530 julius
        l.sfnei r15, 0x2 /* hi-mem counter should be 2 */
643 349 julius
        l.bf _dmmu_test_error
644
        l.nop
645
 
646
        l.lwz r8, 4(r5) /* Should cause DMMU miss, lomem */
647
        /* Check value was OK */
648
        l.sfne r7, r8
649
        l.bf _dmmu_test_error
650
        l.nop
651 530 julius
        l.sfnei r14, 0x3 /* Check for lo mem mapping increment */
652 349 julius
        l.bf _dmmu_test_error
653
        l.nop
654 530 julius
        l.sfnei r15, 0x2 /* hi-mem counter should still be 2 */
655 349 julius
        l.bf _dmmu_test_error
656
        l.nop
657
 
658
        /* Fast DMMU exceptions should follow */
659
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
660
        l.sw 8(r6), r7 /* Should cause DMMU miss, himem */
661
        l.lwz r8, 8(r5) /* Should cause DMMU miss, lomem */
662
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
663
        l.sw 0xc(r6), r7 /* Should cause DMMU miss, himem */
664
        l.lwz r8, 0xc(r5) /* Should cause DMMU miss, lomem */
665
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
666
        l.sw 0x10(r6), r7 /* Should cause DMMU miss, himem */
667
        l.lwz r8, 0x10(r5) /* Should cause DMMU miss, lomem */
668
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
669
        l.sw 0x14(r6), r7 /* Should cause DMMU miss, himem */
670
        l.lwz r8, 0x14(r5) /* Should cause DMMU miss, lomem */
671
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
672
        l.sw 0x18(r6), r7 /* Should cause DMMU miss, himem */
673
        l.lwz r8, 0x18(r5) /* Should cause DMMU miss, lomem */
674
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
675
        l.sw 0x1c(r6), r7 /* Should cause DMMU miss, himem */
676
        l.lwz r8, 0x1c(r5) /* Should cause DMMU miss, lomem */
677
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
678
        l.sw 0x20(r6), r7 /* Should cause DMMU miss, himem */
679
        l.lwz r8, 0x20(r5) /* Should cause DMMU miss, lomem */
680
        l.addi r7, r7, 0x1111 /* Incremement value we're writing */
681
        l.sw 0x24(r6), r7 /* Should cause DMMU miss, himem */
682
        l.lwz r8, 0x24(r5) /* Should cause DMMU miss, lomem */
683
        /* Should now be 11 lowmem DTLB misses and 10 for high memory space */
684
        l.sfne r7, r8
685
        l.bf _dmmu_test_error
686
        l.nop
687 530 julius
        l.sfnei r14, 0xb /* Check for lo mem mapping increment to 11 */
688 349 julius
        l.bf _dmmu_test_error
689
        l.nop
690 530 julius
        l.sfnei r15, 0xa /* hi-mem counter should be 10 */
691 349 julius
        l.bf _dmmu_test_error
692
        l.nop
693
 
694
        l.j _dmmu_test_ok
695
        l.nop
696
 
697
 
698
_dmmu_test_error:
699
        l.movhi r3, hi(0xeeeeeeed)
700
        l.ori r3, r3, lo(0xeeeeeeed)
701
        l.nop 2
702
        l.nop 1
703
 
704
_dmmu_test_ok:
705
        l.nop
706
 
707
#endif // #ifndef OR1200_NO_DMMU
708
 
709
        /* End of tests - report and finish simulation */
710
        l.movhi r3,hi(0xdeaddead)
711
        l.ori   r3,r3,lo(0xdeaddead)
712
        l.nop   2
713
 
714
        l.movhi r3,hi(0x8000000d)
715
        l.ori   r3,r3,lo(0x8000000d)
716
        l.nop   2
717
 
718
        l.addi r3,r0,0
719 373 julius
        l.jal   exit
720 349 julius
        l.nop
721
 
722
 
723
        /* DMMU invalidate function */
724
        /* First parameter, r3, has number of DMMU entries (should be 64)*/
725
 
726
_dmmu_invalidate:
727
        /* Setup the Data MMU's TLBS */
728
        l.movhi r4, hi(SPR_DTLBMR_BASE(0))
729
        l.ori r4, r4, lo(SPR_DTLBMR_BASE(0))
730
 
731
        /* DTLB invalidate loop */
732
1:
733
        l.mtspr r4, r0, 0x0
734
        l.addi r4, r4, 0x1
735
        l.sfeq r3, r0
736
        l.bnf 1b
737
        l.addi r3, r3, -1
738
        l.jr r9
739
        l.nop
740
 

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