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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ext.S] - Blame information for rev 801

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Line No. Rev Author Line
1 499 julius 
/*
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        OR1200 zero and sign extension instruction tests
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        Very basic, testing
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        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
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*/
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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/* =================================================== [ exceptions ] === */
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        .section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        /* Clear status register */
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        l.ori r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Jump to program initialisation code */
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        .global _start
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        l.movhi r4, hi(_start)
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        l.ori r4, r4, lo(_start)
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        l.jr    r4
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        l.nop
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        .org 0x600
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        l.nop 0x1
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/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
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        .org 0x700
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#ifndef OR1200_IMPL_ALU_EXT
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        // No problem - instruction not supported
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        l.movhi r3, hi(0x8000000d)
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        l.ori   r3, r3, lo(0x8000000d)
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        l.nop   0x2
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        l.ori   r3, r0, 0
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#else
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        l.ori   r3, r0, 1
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#endif
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        l.nop   0x1
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/* =================================================== [ text ] === */
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        .section .text
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/* =================================================== [ start ] === */
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        .global _start
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_start:
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        // Kick off test
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        l.jal   _main
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        l.nop
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/* =================================================== [ main ] === */
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        .global _main
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_main:
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        // l.exth tests first
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        l.ori   r4,r0,0xffff
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        l.ori   r5,r0,0x7fff
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        l.exths r3,r4
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        l.movhi r8,0xffff
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        l.ori   r8,r8,0xffff
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        l.nop   0x2
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        l.sfne  r8,r3
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        l.bf    fail
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        l.nop
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        l.ori   r8,r0,0xffff
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        l.exthz r3,r4
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        l.nop   0x2
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        l.sfne  r8,r3
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        l.bf    fail
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        l.nop
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        l.exths r3,r5
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        l.nop   0x2
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        l.sfne  r3,r5
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        l.bf    fail
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        l.nop
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        l.exthz r3,r5
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        l.nop   0x2
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        l.sfne  r3,r5
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        l.bf    fail
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        l.nop
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        // l.extb tests
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        l.ori   r4,r0,0x00ff
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        l.ori   r5,r0,0x007f
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        l.extbs r3,r4
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        l.nop   0x2
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        l.movhi r8,0xffff
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        l.ori   r8,r8,0xffff
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        l.sfne  r8,r3
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        l.bf    fail
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        l.nop
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        l.ori   r8,r0,0x00ff
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        l.extbz r3,r4
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        l.nop   0x2
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        l.sfne  r8,r3
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        l.bf    fail
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        l.nop
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        l.extbs r3,r5
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        l.nop   0x2
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        l.sfne  r3,r5
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        l.bf    fail
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        l.nop
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        l.extbz r3,r5
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        l.nop   0x2
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        l.sfne  r3,r5
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        l.bf    fail
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        l.nop
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        // l.extw tests - shouldn't change anything
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        l.movhi r4,0xffff
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        l.ori   r4,r4,0xffff
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        l.extws r3,r4
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        l.nop   0x2
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        l.sfne  r3,r4
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        l.bf    fail
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        l.nop
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        l.extwz r3,r4
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        l.nop   0x2
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        l.sfne  r3,r4
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        l.bf    fail
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        l.nop
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199 801 julius 
        l.movhi r4,0x7fff
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        l.ori   r4,r4,0xffff
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        l.extws r3,r4
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        l.nop   0x2
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206 801 julius 
        l.sfne  r3,r4
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        l.bf    fail
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        l.nop
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        l.extwz r3,r4
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        l.nop   0x2
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        l.sfne  r3,r4
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        l.bf    fail
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        l.nop
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219 499 julius 
        l.movhi r3, hi(0x8000000d)
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        l.ori   r3, r3, lo(0x8000000d)
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        l.nop   0x2
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        l.ori   r3, r0, 0
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        l.nop   0x1
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fail:
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        l.ori   r3, r0, 1
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        l.nop   0x1

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