URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ffl1.S] - Blame information for rev 499

Details | Compare with Previous | View Log


/*
        OR1200 Find First/Last '1' Test
 
        Checks l.ff1 and l.fl1 outputs for every bit position
 
        Julius Baxter, julius.baxter@orsoc.se
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
 
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
        .org 0x700
#ifndef OR1200_IMPL_ALU_FFL1
        // No problem - instruction not supported
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2
        l.ori   r3, r0, 0
#else
        l.ori   r3, r0, 1
#endif
        l.nop   0x1
 
 
/* =================================================== [ text ] === */
        .section .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
.L10:
        // Kick off test
        l.jal   _main
        l.nop
 
 
 
/* =================================================== [ main ] === */
 
        .global _main
_main:
        l.movhi r3, 0
        l.movhi r4, 0 // Bit we're checking works
        l.movhi r5, 0
        l.ori   r6, r0, 32
        l.movhi r7, 0 // Register we'll put a value in to check with l.ff1
 
#define REPORT(reg)     l.or r3, reg, r0 ; \
                        l.nop 0x2
 
 
ff1_loop:
        // Set a loop going, creating a register with a '1' in a known position
        // and checking the output of the l.ff1
        l.ori   r7, r0, 1       // Put  1 in bit 0
        l.sll   r7, r7, r4      // Shift '1' by r4
        REPORT(r7)              // Report value
        l.ff1   r5, r7          // Do Find First '1' op
        l.fl1   r8, r7          // Do Find Last '1' op
        REPORT(r5)              // Report value
        REPORT(r8)              // Report value
        l.addi  r4, r4, 1       // Increment bit we're checking (will also be
                                // result from l.ff1)
        REPORT(r4)              // Report value
        l.sfne  r5, r4          // r5 should = r4
        l.bf    ff1_error
        l.sfne  r8, r4          // r8 should = r4
        l.bf    fl1_error
        l.sfne  r6, r4          // Check if loop is finished
        l.bf    ff1_loop        // Keep checking
        l.nop
        l.j     ffl1_test2      // All OK, next test
        l.nop
 
ffl1_test2:
        // Try 3 values - all '0', all '1' and a block of values in between
        l.movhi r4, 0
        l.movhi r5, 0xffff
        l.ori   r5, r5,  0xffff
        l.movhi r6, 0x00ff
        l.ori   r6, r6,  0xff00
        // Test '0'
        REPORT(r4)
        l.ff1   r7, r4
        l.fl1   r8, r4
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 0
        l.bf    ff1_error
        l.sfnei r8, 0
        l.bf    fl1_error
 
        // Test '0xffffffff'
        REPORT(r5)
        l.ff1   r7, r5
        l.fl1   r8, r5
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 1
        l.bf    ff1_error
        l.sfnei r8, 32
        l.bf    fl1_error
 
        // Test '0x00ffff00'
        REPORT(r6)
        l.ff1   r7, r6
        l.fl1   r8, r6
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 9
        l.bf    ff1_error
        l.sfnei r8, 24
        l.bf    fl1_error
        l.nop
        l.j ffl1_ok     // Tests OK
 
ff1_error:
        l.movhi r3, hi(0xbaaadff1)
        l.ori    r3, r3, lo(0xbaaadff1)
        l.nop   0x1
 
 
fl1_error:
        l.movhi r3, hi(0xbaaadf11)
        l.ori   r3, r3, lo(0xbaaadf11)
        l.nop   0x1
 
 
ffl1_ok:
 
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2 /* Report */
        l.ori   r3, r0, 0 /* Return 0 */
        l.nop   0x1
 

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ffl1.S] - Blame information for rev 499

Line No.	Rev	Author	Line
1	403	julius	`/*`
2			`OR1200 Find First/Last '1' Test`
3
4			`Checks l.ff1 and l.fl1 outputs for every bit position`
5
6			`Julius Baxter, julius.baxter@orsoc.se`
7
8			`*/`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36
37			`#include "spr-defs.h"`
38			`#include "board.h"`
39			`#include "or1200-defines.h"`
40
41
42			`/* =================================================== [ exceptions ] === */`
43			`.section .vectors, "ax"`
44
45
46			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
47			`.org 0x100`
48			`l.movhi r0, 0`
49			`/* Clear status register */`
50			`l.ori r1, r0, SPR_SR_SM`
51			`l.mtspr r0, r1, SPR_SR`
52			`/* Clear timer */`
53			`l.mtspr r0, r0, SPR_TTMR`
54
55			`/* Jump to program initialisation code */`
56			`.global _start`
57			`l.movhi r4, hi(_start)`
58			`l.ori r4, r4, lo(_start)`
59			`l.jr r4`
60			`l.nop`
61
62	499	julius	`/* ---[ 0x700: Illegal instruction exception ]-------------------------- */`
63			`.org 0x700`
64			`#ifndef OR1200_IMPL_ALU_FFL1`
65			`// No problem - instruction not supported`
66			`l.movhi r3, hi(0x8000000d)`
67			`l.ori r3, r3, lo(0x8000000d)`
68			`l.nop 0x2`
69			`l.ori r3, r0, 0`
70			`#else`
71			`l.ori r3, r0, 1`
72			`#endif`
73			`l.nop 0x1`
74	403	julius
75	499	julius
76	403	julius	`/* =================================================== [ text ] === */`
77			`.section .text`
78
79			`/* =================================================== [ start ] === */`
80
81			`.global _start`
82			`_start:`
83
84			`/* Instruction cache enable */`
85			`/* Check if IC present and skip enabling otherwise */`
86			`l.mfspr r24,r0,SPR_UPR`
87			`l.andi r26,r24,SPR_UPR_ICP`
88			`l.sfeq r26,r0`
89			`l.bf .L8`
90			`l.nop`
91
92			`/* Disable IC */`
93			`l.mfspr r6,r0,SPR_SR`
94			`l.addi r5,r0,-1`
95			`l.xori r5,r5,SPR_SR_ICE`
96			`l.and r5,r6,r5`
97			`l.mtspr r0,r5,SPR_SR`
98
99			`/* Establish cache block size`
100			`If BS=0, 16;`
101			`If BS=1, 32;`
102			`r14 contain block size`
103			`*/`
104			`l.mfspr r24,r0,SPR_ICCFGR`
105			`l.andi r26,r24,SPR_ICCFGR_CBS`
106			`l.srli r28,r26,7`
107			`l.ori r30,r0,16`
108			`l.sll r14,r30,r28`
109
110			`/* Establish number of cache sets`
111			`r16 contains number of cache sets`
112			`r28 contains log(# of cache sets)`
113			`*/`
114			`l.andi r26,r24,SPR_ICCFGR_NCS`
115			`l.srli r28,r26,3`
116			`l.ori r30,r0,1`
117			`l.sll r16,r30,r28`
118
119			`/* Invalidate IC */`
120			`l.addi r6,r0,0`
121			`l.sll r5,r14,r28`
122
123			`.L7:`
124			`l.mtspr r0,r6,SPR_ICBIR`
125			`l.sfne r6,r5`
126			`l.bf .L7`
127			`l.add r6,r6,r14`
128
129			`/* Enable IC */`
130			`l.mfspr r6,r0,SPR_SR`
131			`l.ori r6,r6,SPR_SR_ICE`
132			`l.mtspr r0,r6,SPR_SR`
133			`l.nop`
134			`l.nop`
135			`l.nop`
136			`l.nop`
137			`l.nop`
138			`l.nop`
139			`l.nop`
140			`l.nop`
141
142			`.L8:`
143			`/* Data cache enable */`
144			`/* Check if DC present and skip enabling otherwise */`
145			`l.mfspr r24,r0,SPR_UPR`
146			`l.andi r26,r24,SPR_UPR_DCP`
147			`l.sfeq r26,r0`
148			`l.bf .L10`
149			`l.nop`
150			`/* Disable DC */`
151			`l.mfspr r6,r0,SPR_SR`
152			`l.addi r5,r0,-1`
153			`l.xori r5,r5,SPR_SR_DCE`
154			`l.and r5,r6,r5`
155			`l.mtspr r0,r5,SPR_SR`
156			`/* Establish cache block size`
157			`If BS=0, 16;`
158			`If BS=1, 32;`
159			`r14 contain block size`
160			`*/`
161			`l.mfspr r24,r0,SPR_DCCFGR`
162			`l.andi r26,r24,SPR_DCCFGR_CBS`
163			`l.srli r28,r26,7`
164			`l.ori r30,r0,16`
165			`l.sll r14,r30,r28`
166			`/* Establish number of cache sets`
167			`r16 contains number of cache sets`
168			`r28 contains log(# of cache sets)`
169			`*/`
170			`l.andi r26,r24,SPR_DCCFGR_NCS`
171			`l.srli r28,r26,3`
172			`l.ori r30,r0,1`
173			`l.sll r16,r30,r28`
174			`/* Invalidate DC */`
175			`l.addi r6,r0,0`
176			`l.sll r5,r14,r28`
177			`.L9:`
178			`l.mtspr r0,r6,SPR_DCBIR`
179			`l.sfne r6,r5`
180			`l.bf .L9`
181			`l.add r6,r6,r14`
182			`/* Enable DC */`
183			`l.mfspr r6,r0,SPR_SR`
184			`l.ori r6,r6,SPR_SR_DCE`
185			`l.mtspr r0,r6,SPR_SR`
186			`.L10:`
187			`// Kick off test`
188			`l.jal _main`
189			`l.nop`
190
191
192
193			`/* =================================================== [ main ] === */`
194
195			`.global _main`
196			`_main:`
197			`l.movhi r3, 0`
198			`l.movhi r4, 0 // Bit we're checking works`
199			`l.movhi r5, 0`
200			`l.ori r6, r0, 32`
201			`l.movhi r7, 0 // Register we'll put a value in to check with l.ff1`
202
203			`#define REPORT(reg) l.or r3, reg, r0 ; \`
204			`l.nop 0x2`
205
206
207			`ff1_loop:`
208			`// Set a loop going, creating a register with a '1' in a known position`
209			`// and checking the output of the l.ff1`
210			`l.ori r7, r0, 1 // Put 1 in bit 0`
211			`l.sll r7, r7, r4 // Shift '1' by r4`
212			`REPORT(r7) // Report value`
213			`l.ff1 r5, r7 // Do Find First '1' op`
214			`l.fl1 r8, r7 // Do Find Last '1' op`
215			`REPORT(r5) // Report value`
216			`REPORT(r8) // Report value`
217			`l.addi r4, r4, 1 // Increment bit we're checking (will also be`
218			`// result from l.ff1)`
219			`REPORT(r4) // Report value`
220			`l.sfne r5, r4 // r5 should = r4`
221			`l.bf ff1_error`
222			`l.sfne r8, r4 // r8 should = r4`
223			`l.bf fl1_error`
224			`l.sfne r6, r4 // Check if loop is finished`
225			`l.bf ff1_loop // Keep checking`
226			`l.nop`
227			`l.j ffl1_test2 // All OK, next test`
228			`l.nop`
229
230			`ffl1_test2:`
231			`// Try 3 values - all '0', all '1' and a block of values in between`
232			`l.movhi r4, 0`
233			`l.movhi r5, 0xffff`
234			`l.ori r5, r5, 0xffff`
235			`l.movhi r6, 0x00ff`
236			`l.ori r6, r6, 0xff00`
237			`// Test '0'`
238			`REPORT(r4)`
239			`l.ff1 r7, r4`
240			`l.fl1 r8, r4`
241			`REPORT(r7)`
242			`REPORT(r8)`
243			`l.sfnei r7, 0`
244			`l.bf ff1_error`
245			`l.sfnei r8, 0`
246			`l.bf fl1_error`
247
248			`// Test '0xffffffff'`
249			`REPORT(r5)`
250			`l.ff1 r7, r5`
251			`l.fl1 r8, r5`
252			`REPORT(r7)`
253			`REPORT(r8)`
254			`l.sfnei r7, 1`
255			`l.bf ff1_error`
256			`l.sfnei r8, 32`
257			`l.bf fl1_error`
258
259			`// Test '0x00ffff00'`
260			`REPORT(r6)`
261			`l.ff1 r7, r6`
262			`l.fl1 r8, r6`
263			`REPORT(r7)`
264			`REPORT(r8)`
265			`l.sfnei r7, 9`
266			`l.bf ff1_error`
267			`l.sfnei r8, 24`
268			`l.bf fl1_error`
269			`l.nop`
270			`l.j ffl1_ok // Tests OK`
271
272			`ff1_error:`
273			`l.movhi r3, hi(0xbaaadff1)`
274			`l.ori r3, r3, lo(0xbaaadff1)`
275			`l.nop 0x1`
276
277
278			`fl1_error:`
279			`l.movhi r3, hi(0xbaaadf11)`
280	425	julius	`l.ori r3, r3, lo(0xbaaadf11)`
281	403	julius	`l.nop 0x1`
282
283
284			`ffl1_ok:`
285
286			`l.movhi r3, hi(0x8000000d)`
287	425	julius	`l.ori r3, r3, lo(0x8000000d)`
288			`l.nop 0x2 /* Report */`
289			`l.ori r3, r0, 0 /* Return 0 */`
290			`l.nop 0x1`
291	403	julius