URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ffl1.S] - Blame information for rev 425

Details | Compare with Previous | View Log


/*
        OR1200 Find First/Last '1' Test
 
        Checks l.ff1 and l.fl1 outputs for every bit position
 
        Julius Baxter, julius.baxter@orsoc.se
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"
 
// Check MAC unit is enabled before trying to run this test
#ifndef OR1200_IMPL_ALU_FFL1
# error
# error Find First/Last '1' isntructions not enabled.
# error
#endif
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
 
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* =================================================== [ text ] === */
        .section .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
.L10:
        // Kick off test
        l.jal   _main
        l.nop
 
 
 
/* =================================================== [ main ] === */
 
        .global _main
_main:
        l.movhi r3, 0
        l.movhi r4, 0 // Bit we're checking works
        l.movhi r5, 0
        l.ori   r6, r0, 32
        l.movhi r7, 0 // Register we'll put a value in to check with l.ff1
 
#define REPORT(reg)     l.or r3, reg, r0 ; \
                        l.nop 0x2
 
 
ff1_loop:
        // Set a loop going, creating a register with a '1' in a known position
        // and checking the output of the l.ff1
        l.ori   r7, r0, 1       // Put  1 in bit 0
        l.sll   r7, r7, r4      // Shift '1' by r4
        REPORT(r7)              // Report value
        l.ff1   r5, r7          // Do Find First '1' op
        l.fl1   r8, r7          // Do Find Last '1' op
        REPORT(r5)              // Report value
        REPORT(r8)              // Report value
        l.addi  r4, r4, 1       // Increment bit we're checking (will also be
                                // result from l.ff1)
        REPORT(r4)              // Report value
        l.sfne  r5, r4          // r5 should = r4
        l.bf    ff1_error
        l.sfne  r8, r4          // r8 should = r4
        l.bf    fl1_error
        l.sfne  r6, r4          // Check if loop is finished
        l.bf    ff1_loop        // Keep checking
        l.nop
        l.j     ffl1_test2      // All OK, next test
        l.nop
 
ffl1_test2:
        // Try 3 values - all '0', all '1' and a block of values in between
        l.movhi r4, 0
        l.movhi r5, 0xffff
        l.ori   r5, r5,  0xffff
        l.movhi r6, 0x00ff
        l.ori   r6, r6,  0xff00
        // Test '0'
        REPORT(r4)
        l.ff1   r7, r4
        l.fl1   r8, r4
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 0
        l.bf    ff1_error
        l.sfnei r8, 0
        l.bf    fl1_error
 
        // Test '0xffffffff'
        REPORT(r5)
        l.ff1   r7, r5
        l.fl1   r8, r5
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 1
        l.bf    ff1_error
        l.sfnei r8, 32
        l.bf    fl1_error
 
        // Test '0x00ffff00'
        REPORT(r6)
        l.ff1   r7, r6
        l.fl1   r8, r6
        REPORT(r7)
        REPORT(r8)
        l.sfnei r7, 9
        l.bf    ff1_error
        l.sfnei r8, 24
        l.bf    fl1_error
        l.nop
        l.j ffl1_ok     // Tests OK
 
ff1_error:
        l.movhi r3, hi(0xbaaadff1)
        l.ori    r3, r3, lo(0xbaaadff1)
        l.nop   0x1
 
 
fl1_error:
        l.movhi r3, hi(0xbaaadf11)
        l.ori   r3, r3, lo(0xbaaadf11)
        l.nop   0x1
 
 
ffl1_ok:
 
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2 /* Report */
        l.ori   r3, r0, 0 /* Return 0 */
        l.nop   0x1
 

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ffl1.S] - Blame information for rev 425

Line No.	Rev	Author	Line
1	403	julius	`/*`
2			`OR1200 Find First/Last '1' Test`
3
4			`Checks l.ff1 and l.fl1 outputs for every bit position`
5
6			`Julius Baxter, julius.baxter@orsoc.se`
7
8			`*/`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36
37			`#include "spr-defs.h"`
38			`#include "board.h"`
39			`#include "or1200-defines.h"`
40
41			`// Check MAC unit is enabled before trying to run this test`
42			`#ifndef OR1200_IMPL_ALU_FFL1`
43			`# error`
44			`# error Find First/Last '1' isntructions not enabled.`
45			`# error`
46			`#endif`
47
48
49			`/* =================================================== [ exceptions ] === */`
50			`.section .vectors, "ax"`
51
52
53			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
54			`.org 0x100`
55			`l.movhi r0, 0`
56			`/* Clear status register */`
57			`l.ori r1, r0, SPR_SR_SM`
58			`l.mtspr r0, r1, SPR_SR`
59			`/* Clear timer */`
60			`l.mtspr r0, r0, SPR_TTMR`
61
62			`/* Jump to program initialisation code */`
63			`.global _start`
64			`l.movhi r4, hi(_start)`
65			`l.ori r4, r4, lo(_start)`
66			`l.jr r4`
67			`l.nop`
68
69
70			`/* =================================================== [ text ] === */`
71			`.section .text`
72
73			`/* =================================================== [ start ] === */`
74
75			`.global _start`
76			`_start:`
77
78			`/* Instruction cache enable */`
79			`/* Check if IC present and skip enabling otherwise */`
80			`l.mfspr r24,r0,SPR_UPR`
81			`l.andi r26,r24,SPR_UPR_ICP`
82			`l.sfeq r26,r0`
83			`l.bf .L8`
84			`l.nop`
85
86			`/* Disable IC */`
87			`l.mfspr r6,r0,SPR_SR`
88			`l.addi r5,r0,-1`
89			`l.xori r5,r5,SPR_SR_ICE`
90			`l.and r5,r6,r5`
91			`l.mtspr r0,r5,SPR_SR`
92
93			`/* Establish cache block size`
94			`If BS=0, 16;`
95			`If BS=1, 32;`
96			`r14 contain block size`
97			`*/`
98			`l.mfspr r24,r0,SPR_ICCFGR`
99			`l.andi r26,r24,SPR_ICCFGR_CBS`
100			`l.srli r28,r26,7`
101			`l.ori r30,r0,16`
102			`l.sll r14,r30,r28`
103
104			`/* Establish number of cache sets`
105			`r16 contains number of cache sets`
106			`r28 contains log(# of cache sets)`
107			`*/`
108			`l.andi r26,r24,SPR_ICCFGR_NCS`
109			`l.srli r28,r26,3`
110			`l.ori r30,r0,1`
111			`l.sll r16,r30,r28`
112
113			`/* Invalidate IC */`
114			`l.addi r6,r0,0`
115			`l.sll r5,r14,r28`
116
117			`.L7:`
118			`l.mtspr r0,r6,SPR_ICBIR`
119			`l.sfne r6,r5`
120			`l.bf .L7`
121			`l.add r6,r6,r14`
122
123			`/* Enable IC */`
124			`l.mfspr r6,r0,SPR_SR`
125			`l.ori r6,r6,SPR_SR_ICE`
126			`l.mtspr r0,r6,SPR_SR`
127			`l.nop`
128			`l.nop`
129			`l.nop`
130			`l.nop`
131			`l.nop`
132			`l.nop`
133			`l.nop`
134			`l.nop`
135
136			`.L8:`
137			`/* Data cache enable */`
138			`/* Check if DC present and skip enabling otherwise */`
139			`l.mfspr r24,r0,SPR_UPR`
140			`l.andi r26,r24,SPR_UPR_DCP`
141			`l.sfeq r26,r0`
142			`l.bf .L10`
143			`l.nop`
144			`/* Disable DC */`
145			`l.mfspr r6,r0,SPR_SR`
146			`l.addi r5,r0,-1`
147			`l.xori r5,r5,SPR_SR_DCE`
148			`l.and r5,r6,r5`
149			`l.mtspr r0,r5,SPR_SR`
150			`/* Establish cache block size`
151			`If BS=0, 16;`
152			`If BS=1, 32;`
153			`r14 contain block size`
154			`*/`
155			`l.mfspr r24,r0,SPR_DCCFGR`
156			`l.andi r26,r24,SPR_DCCFGR_CBS`
157			`l.srli r28,r26,7`
158			`l.ori r30,r0,16`
159			`l.sll r14,r30,r28`
160			`/* Establish number of cache sets`
161			`r16 contains number of cache sets`
162			`r28 contains log(# of cache sets)`
163			`*/`
164			`l.andi r26,r24,SPR_DCCFGR_NCS`
165			`l.srli r28,r26,3`
166			`l.ori r30,r0,1`
167			`l.sll r16,r30,r28`
168			`/* Invalidate DC */`
169			`l.addi r6,r0,0`
170			`l.sll r5,r14,r28`
171			`.L9:`
172			`l.mtspr r0,r6,SPR_DCBIR`
173			`l.sfne r6,r5`
174			`l.bf .L9`
175			`l.add r6,r6,r14`
176			`/* Enable DC */`
177			`l.mfspr r6,r0,SPR_SR`
178			`l.ori r6,r6,SPR_SR_DCE`
179			`l.mtspr r0,r6,SPR_SR`
180			`.L10:`
181			`// Kick off test`
182			`l.jal _main`
183			`l.nop`
184
185
186
187			`/* =================================================== [ main ] === */`
188
189			`.global _main`
190			`_main:`
191			`l.movhi r3, 0`
192			`l.movhi r4, 0 // Bit we're checking works`
193			`l.movhi r5, 0`
194			`l.ori r6, r0, 32`
195			`l.movhi r7, 0 // Register we'll put a value in to check with l.ff1`
196
197			`#define REPORT(reg) l.or r3, reg, r0 ; \`
198			`l.nop 0x2`
199
200
201			`ff1_loop:`
202			`// Set a loop going, creating a register with a '1' in a known position`
203			`// and checking the output of the l.ff1`
204			`l.ori r7, r0, 1 // Put 1 in bit 0`
205			`l.sll r7, r7, r4 // Shift '1' by r4`
206			`REPORT(r7) // Report value`
207			`l.ff1 r5, r7 // Do Find First '1' op`
208			`l.fl1 r8, r7 // Do Find Last '1' op`
209			`REPORT(r5) // Report value`
210			`REPORT(r8) // Report value`
211			`l.addi r4, r4, 1 // Increment bit we're checking (will also be`
212			`// result from l.ff1)`
213			`REPORT(r4) // Report value`
214			`l.sfne r5, r4 // r5 should = r4`
215			`l.bf ff1_error`
216			`l.sfne r8, r4 // r8 should = r4`
217			`l.bf fl1_error`
218			`l.sfne r6, r4 // Check if loop is finished`
219			`l.bf ff1_loop // Keep checking`
220			`l.nop`
221			`l.j ffl1_test2 // All OK, next test`
222			`l.nop`
223
224			`ffl1_test2:`
225			`// Try 3 values - all '0', all '1' and a block of values in between`
226			`l.movhi r4, 0`
227			`l.movhi r5, 0xffff`
228			`l.ori r5, r5, 0xffff`
229			`l.movhi r6, 0x00ff`
230			`l.ori r6, r6, 0xff00`
231			`// Test '0'`
232			`REPORT(r4)`
233			`l.ff1 r7, r4`
234			`l.fl1 r8, r4`
235			`REPORT(r7)`
236			`REPORT(r8)`
237			`l.sfnei r7, 0`
238			`l.bf ff1_error`
239			`l.sfnei r8, 0`
240			`l.bf fl1_error`
241
242			`// Test '0xffffffff'`
243			`REPORT(r5)`
244			`l.ff1 r7, r5`
245			`l.fl1 r8, r5`
246			`REPORT(r7)`
247			`REPORT(r8)`
248			`l.sfnei r7, 1`
249			`l.bf ff1_error`
250			`l.sfnei r8, 32`
251			`l.bf fl1_error`
252
253			`// Test '0x00ffff00'`
254			`REPORT(r6)`
255			`l.ff1 r7, r6`
256			`l.fl1 r8, r6`
257			`REPORT(r7)`
258			`REPORT(r8)`
259			`l.sfnei r7, 9`
260			`l.bf ff1_error`
261			`l.sfnei r8, 24`
262			`l.bf fl1_error`
263			`l.nop`
264			`l.j ffl1_ok // Tests OK`
265
266			`ff1_error:`
267			`l.movhi r3, hi(0xbaaadff1)`
268			`l.ori r3, r3, lo(0xbaaadff1)`
269			`l.nop 0x1`
270
271
272			`fl1_error:`
273			`l.movhi r3, hi(0xbaaadf11)`
274	425	julius	`l.ori r3, r3, lo(0xbaaadf11)`
275	403	julius	`l.nop 0x1`
276
277
278			`ffl1_ok:`
279
280			`l.movhi r3, hi(0x8000000d)`
281	425	julius	`l.ori r3, r3, lo(0x8000000d)`
282			`l.nop 0x2 /* Report */`
283			`l.ori r3, r0, 0 /* Return 0 */`
284			`l.nop 0x1`
285	403	julius