URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-intsyscall.S] - Blame information for rev 661

Go to most recent revision | Details | Compare with Previous | View Log


#include "spr-defs.h"
#include "board.h"
 
/*
 
        User IRQ and system call simultaneous interrupt test
 
        Within the test we'll use following global variables:
 
        r15 syscall interrupt counter
        r6 syscall function counter
        r10 irq interrupt counter
        r12 intgen's base address
 
 
        The test does the following:
        Uses the intgen module to schedule interrupts to see if they clash
        with system calls.
 
        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global _stack
        l.movhi r1, hi(_stack)
        l.ori   r1, r1, lo(_stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* =================================================== [ User interrupt ] === */
        .org 0x800
        .global _user_irq_handler
_user_irq_handler:
        l.addi r10, r10, 1
        /* Report values , 0x00000800 == user interrupt report*/
        l.ori r3, r0, 0x0800
        l.nop 2
        l.or r3, r0, r10
        l.nop 2
        /* TODO - propably confirm it was intgen's IRQ that caused this */
        /* Clear interrupt source */
        l.ori   r7, r12, 0x1    /* intgen IRQ clear address */
        l.sb    0(r7), r0       /* Any write clears the bit */
        /* Clear OR1200 PICSR */
        l.mfspr r7, r0, SPR_PICSR
        l.mtspr r0, r7, SPR_PICSR
 
        l.rfe
 
/* ========================================================= [ syscall ] === */
        .org 0xC00
        .extern _syscall_function
        .global _syscall_handler
_syscall_handler:
        l.addi r15, r15, 1
        l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */
        l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/
        /* Unset IEE and TEE bits of SR */
        l.ori r4, r0, SPR_SR_IEE|SPR_SR_TEE
        l.ori r5, r0, 0xffff
        l.xor r5, r5, r4
        l.and r5, r7, r5 /* New SR without interrupt bits set */
        l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */
        /* Report values , 0x00000c00 == system call report*/
        l.ori r3, r0, 0x0c00
        l.nop 2
        /* Get syscall number */
        l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */
        l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */
        l.nop 2
        l.movhi r4, hi(_syscall_function)
        l.ori r4, r4, lo(_syscall_function)
        l.mtspr r0, r4, SPR_EPCR_BASE
        l.rfe
 
 
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
        // Kick off test
        l.jal   _main
        l.nop
 
/* =================================================== [ main ] === */
.global _main
_main:
 
        #
        # unmask (enable) all ints
        #
        l.movhi r5,0xffff
        l.ori   r5,r5,0xffff
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
 
        /* Enable Interrupts */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_IEE
        l.mtspr r0,r6,SPR_SR
 
        l.movhi r15, 0
        l.movhi r6, 0
        l.movhi r10, 0
 
 
 
        // Assumes r12 is intgen's base address
        l.movhi r12,hi(INTGEN_BASE)
 
#define INTGEN_LOAD(x)  \
        l.ori   r5,r0,lo(x)     ;\
        l.sb    0(r12),r5
 
 
        /* Test begin */
 
        l.nop
        INTGEN_LOAD(1)
        l.sys 0x1
        l.nop
        INTGEN_LOAD(1)
        l.nop
        l.sys 0x2
        l.nop
        INTGEN_LOAD(2)
        l.sys 0x3
        l.nop
        INTGEN_LOAD(2)
        l.nop
        l.sys 0x4
        l.nop
        l.ori   r5,r0,1
        l.sys 0x5
        l.sb    0(r12),r5
        l.nop
        l.nop
        l.nop
        l.sfnei r6, 0xf /* Should equal 15, 0xf */
        l.bf _fail
        l.nop
 
        l.movhi r3, hi(0x8000000d)
        l.ori r3, r3, lo(0x8000000d)
        l.nop 2
        l.ori r3, r0, 0
        l.nop 1
 
_fail:
        l.movhi r3, hi(0xbaaaaaad)
        l.ori r3, r3, lo(0xbaaaaaad)
        l.nop 1
 
        .global _syscall_function
_syscall_function:
        /* r7 and r8 hold actual real ESR and EPCR, respectively */
        /* We'll restore them now */
        l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */
        l.mtspr r0, r8, SPR_EPCR_BASE
        l.add r6, r6, r3 /* Add syscall number to our counter */
        l.movhi r4, hi(0x00400000) /* 4MB mark of memory */
        /* Ensure memory access OK */
        l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */
        l.add r4, r4, r3 /* Access this offset from 4MB mark */
        l.sw 0(r4), r6 /* Do a write to memory */
        l.lwz r6, 0(r4) /* Do a read from memory */
        /* Report running value of syscall counter */
        l.or r3, r0, r6
        l.nop 2
        l.rfe /* Now continue from where we had the l.sys */
 

Line No.	Rev	Author	Line
1	506	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`/*`
5
6			`User IRQ and system call simultaneous interrupt test`
7
8			`Within the test we'll use following global variables:`
9
10			`r15 syscall interrupt counter`
11	530	julius	`r6 syscall function counter`
12			`r10 irq interrupt counter`
13			`r12 intgen's base address`
14	506	julius
15
16			`The test does the following:`
17			`Uses the intgen module to schedule interrupts to see if they clash`
18			`with system calls.`
19
20			`Julius Baxter, ORSoC AB, julius.baxter@orsoc.se`
21			`*/`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2011 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48
49
50			`/* =================================================== [ exceptions ] === */`
51			`.section .vectors, "ax"`
52
53
54			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
55			`.org 0x100`
56			`l.movhi r0, 0`
57			`/* Clear status register */`
58			`l.ori r1, r0, SPR_SR_SM`
59			`l.mtspr r0, r1, SPR_SR`
60			`/* Clear timer */`
61			`l.mtspr r0, r0, SPR_TTMR`
62			`/* Init the stack */`
63			`.global _stack`
64			`l.movhi r1, hi(_stack)`
65			`l.ori r1, r1, lo(_stack)`
66			`l.addi r2, r0, -3`
67			`l.and r1, r1, r2`
68			`/* Jump to program initialisation code */`
69			`.global _start`
70			`l.movhi r4, hi(_start)`
71			`l.ori r4, r4, lo(_start)`
72			`l.jr r4`
73			`l.nop`
74
75
76			`/* =================================================== [ User interrupt ] === */`
77			`.org 0x800`
78			`.global _user_irq_handler`
79			`_user_irq_handler:`
80	530	julius	`l.addi r10, r10, 1`
81	506	julius	`/* Report values , 0x00000800 == user interrupt report*/`
82			`l.ori r3, r0, 0x0800`
83			`l.nop 2`
84	530	julius	`l.or r3, r0, r10`
85	506	julius	`l.nop 2`
86			`/* TODO - propably confirm it was intgen's IRQ that caused this */`
87			`/* Clear interrupt source */`
88	530	julius	`l.ori r7, r12, 0x1 /* intgen IRQ clear address */`
89	506	julius	`l.sb 0(r7), r0 /* Any write clears the bit */`
90			`/* Clear OR1200 PICSR */`
91			`l.mfspr r7, r0, SPR_PICSR`
92			`l.mtspr r0, r7, SPR_PICSR`
93
94			`l.rfe`
95
96			`/* ========================================================= [ syscall ] === */`
97			`.org 0xC00`
98			`.extern _syscall_function`
99			`.global _syscall_handler`
100			`_syscall_handler:`
101			`l.addi r15, r15, 1`
102			`l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */`
103			`l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/`
104			`/* Unset IEE and TEE bits of SR */`
105			`l.ori r4, r0, SPR_SR_IEE\|SPR_SR_TEE`
106			`l.ori r5, r0, 0xffff`
107			`l.xor r5, r5, r4`
108			`l.and r5, r7, r5 /* New SR without interrupt bits set */`
109			`l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */`
110	530	julius	`/* Report values , 0x00000c00 == system call report*/`
111	506	julius	`l.ori r3, r0, 0x0c00`
112			`l.nop 2`
113			`/* Get syscall number */`
114			`l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */`
115			`l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */`
116			`l.nop 2`
117			`l.movhi r4, hi(_syscall_function)`
118			`l.ori r4, r4, lo(_syscall_function)`
119			`l.mtspr r0, r4, SPR_EPCR_BASE`
120			`l.rfe`
121
122
123
124			`/* =================================================== [ text section ] === */`
125			`.section .text`
126
127			`/* =================================================== [ start ] === */`
128
129			`.global _start`
130			`_start:`
131			`// Kick off test`
132			`l.jal _main`
133			`l.nop`
134
135			`/* =================================================== [ main ] === */`
136			`.global _main`
137			`_main:`
138
139			`#`
140			`# unmask (enable) all ints`
141			`#`
142			`l.movhi r5,0xffff`
143			`l.ori r5,r5,0xffff`
144			`l.mtspr r0,r5,SPR_PICMR # set PICMR`
145
146			`/* Enable Interrupts */`
147			`l.mfspr r6,r0,SPR_SR`
148			`l.ori r6,r6,SPR_SR_IEE`
149			`l.mtspr r0,r6,SPR_SR`
150
151	530	julius	`l.movhi r15, 0`
152			`l.movhi r6, 0`
153			`l.movhi r10, 0`
154
155
156	506	julius
157	530	julius	`// Assumes r12 is intgen's base address`
158			`l.movhi r12,hi(INTGEN_BASE)`
159	506	julius
160			`#define INTGEN_LOAD(x) \`
161			`l.ori r5,r0,lo(x) ;\`
162	530	julius	`l.sb 0(r12),r5`
163	506	julius
164
165			`/* Test begin */`
166
167			`l.nop`
168			`INTGEN_LOAD(1)`
169			`l.sys 0x1`
170			`l.nop`
171			`INTGEN_LOAD(1)`
172			`l.nop`
173			`l.sys 0x2`
174			`l.nop`
175			`INTGEN_LOAD(2)`
176			`l.sys 0x3`
177			`l.nop`
178			`INTGEN_LOAD(2)`
179			`l.nop`
180			`l.sys 0x4`
181			`l.nop`
182			`l.ori r5,r0,1`
183			`l.sys 0x5`
184	530	julius	`l.sb 0(r12),r5`
185	506	julius	`l.nop`
186			`l.nop`
187			`l.nop`
188	530	julius	`l.sfnei r6, 0xf /* Should equal 15, 0xf */`
189	506	julius	`l.bf _fail`
190			`l.nop`
191
192			`l.movhi r3, hi(0x8000000d)`
193			`l.ori r3, r3, lo(0x8000000d)`
194			`l.nop 2`
195			`l.ori r3, r0, 0`
196			`l.nop 1`
197
198			`_fail:`
199			`l.movhi r3, hi(0xbaaaaaad)`
200			`l.ori r3, r3, lo(0xbaaaaaad)`
201			`l.nop 1`
202
203			`.global _syscall_function`
204			`_syscall_function:`
205			`/* r7 and r8 hold actual real ESR and EPCR, respectively */`
206			`/* We'll restore them now */`
207			`l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */`
208			`l.mtspr r0, r8, SPR_EPCR_BASE`
209	530	julius	`l.add r6, r6, r3 /* Add syscall number to our counter */`
210	506	julius	`l.movhi r4, hi(0x00400000) /* 4MB mark of memory */`
211			`/* Ensure memory access OK */`
212			`l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */`
213			`l.add r4, r4, r3 /* Access this offset from 4MB mark */`
214	530	julius	`l.sw 0(r4), r6 /* Do a write to memory */`
215			`l.lwz r6, 0(r4) /* Do a read from memory */`
216	506	julius	`/* Report running value of syscall counter */`
217	530	julius	`l.or r3, r0, r6`
218	506	julius	`l.nop 2`
219			`l.rfe /* Now continue from where we had the l.sys */`
220

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-intsyscall.S] - Blame information for rev 661