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349 |
julius |
/*
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Tests of link register behavior in delay slot of l.jal instruction
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Testing this:
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l.jal _place
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l.sw 4(r1) r9
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What happens...... (r9 is link register)
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Result:
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Appears to confirm that the r9 becomes the return value immediately
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( at the write-back stage of the l.jal instruction)
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Then testing this:
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l.jal _place
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l.or r9, r0, r0
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Result:
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Writing to link register (r9) in delay slot works, so should be
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avoided (it was illegal according to spec, anyway)
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Init the stack */
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.global _stack
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l.movhi r1, hi(_stack)
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l.ori r1, r1, lo(_stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* =================================================== [ text ] === */
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.section .text
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/* =================================================== [ start ] === */
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.global _start
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.global _testjalfunc
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_start:
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l.addi r1, r1, -4
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l.movhi r9, hi(0x01234567)
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l.ori r9, r9, lo(0x01234567)
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l.or r3, r1, r1 /* copy stack pointer to r3 so we can report it */
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l.nop 0x2
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l.jal _testjalfunc
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l.sw 0(r1), r9
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l.nop
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l.nop
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l.movhi r3, hi(0x8000000d)
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l.ori r3, r3, lo(0x8000000d)
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425 |
julius |
/* Setup some code at address 0x0 */
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349 |
julius |
l.movhi r4, hi(0x15000000) /* standard l.nop */
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425 |
julius |
l.ori r5, r4, 0x2 /* l.nop that will report value in r3 */
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l.sw 0x0(r0), r5 /* Write "l.nop 0x2" to 0x0 */
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l.movhi r6, hi(0xa8600000) /*Assemble register with l.ori r3,r0,0 */
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l.sw 0x4(r0), r6 /* Write "l.ori r3,r0,0" to 0x4*/
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349 |
julius |
l.ori r5, r4, 0x1 /* l.nop that will exit simulation */
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425 |
julius |
l.sw 0x8(r0), r5 /* Write l.nop 0x1 to 0x8 */
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l.sw 0xc(r0), r0 /* Write "l.j 0" to address 0xc */
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l.sw 0x10(r0), r4 /* Write l.nop to 0xc */
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349 |
julius |
l.nop
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425 |
julius |
/* Try writing to r9 during delay slot... */
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349 |
julius |
l.jal _testjalfunc
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425 |
julius |
l.or r9, r0, r0 /* Clear r9 - cause jump to 0 on return */
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349 |
julius |
l.nop 1
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_testjalfunc:
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.jr r9
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l.nop
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