OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-mac.S] - Blame information for rev 393

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 356 julius 
/*
2 
        OR1200 MAC test
3 
 
4 
        Very basic, testing simple instructions and multiplication,
5 
        accumulation values
6 
 
7 
        Julius Baxter, julius.baxter@orsoc.se
8 
 
9 
*/
10 
//////////////////////////////////////////////////////////////////////
11 
////                                                              ////
12 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
13 
////                                                              ////
14 
//// This source file may be used and distributed without         ////
15 
//// restriction provided that this copyright statement is not    ////
16 
//// removed from the file and that any derivative work contains  ////
17 
//// the original copyright notice and the associated disclaimer. ////
18 
////                                                              ////
19 
//// This source file is free software; you can redistribute it   ////
20 
//// and/or modify it under the terms of the GNU Lesser General   ////
21 
//// Public License as published by the Free Software Foundation; ////
22 
//// either version 2.1 of the License, or (at your option) any   ////
23 
//// later version.                                               ////
24 
////                                                              ////
25 
//// This source is distributed in the hope that it will be       ////
26 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
27 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
28 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
29 
//// details.                                                     ////
30 
////                                                              ////
31 
//// You should have received a copy of the GNU Lesser General    ////
32 
//// Public License along with this source; if not, download it   ////
33 
//// from http://www.opencores.org/lgpl.shtml                     ////
34 
////                                                              ////
35 
//////////////////////////////////////////////////////////////////////
36 
 
37 
 
38 
#include "spr-defs.h"
39 
#include "board.h"
40 
#include "or1200-defines.h"
41 
 
42 
// Check MAC unit is enabled before trying to run this test
43 
#ifndef OR1200_MAC_IMPLEMENTED
44 
# error
45 
# error No MAC unit detected. This test requires hardware MAC support
46 
# error
47 
#endif
48 
 
49 
 
50 
/* =================================================== [ exceptions ] === */
51 
        .section .vectors, "ax"
52 
 
53 
 
54 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
55 
        .org 0x100
56 
        l.movhi r0, 0
57 
        /* Clear status register */
58 
        l.ori r1, r0, SPR_SR_SM
59 
        l.mtspr r0, r1, SPR_SR
60 
        /* Clear timer  */
61 
        l.mtspr r0, r0, SPR_TTMR
62 
 
63 
        /* Jump to program initialisation code */
64 
        .global _start
65 
        l.movhi r4, hi(_start)
66 
        l.ori r4, r4, lo(_start)
67 
        l.jr    r4
68 
        l.nop
69 
 
70 
 
71 
/* =================================================== [ text ] === */
72 
        .section .text
73 
 
74 
/* =================================================== [ start ] === */
75 
 
76 
        .global _start
77 
_start:
78 
 
79 
        /* Instruction cache enable */
80 
        /* Check if IC present and skip enabling otherwise */
81 
        l.mfspr r24,r0,SPR_UPR
82 
        l.andi  r26,r24,SPR_UPR_ICP
83 
        l.sfeq  r26,r0
84 
        l.bf    .L8
85 
        l.nop
86 
 
87 
        /* Disable IC */
88 
        l.mfspr r6,r0,SPR_SR
89 
        l.addi  r5,r0,-1
90 
        l.xori  r5,r5,SPR_SR_ICE
91 
        l.and   r5,r6,r5
92 
        l.mtspr r0,r5,SPR_SR
93 
 
94 
        /* Establish cache block size
95 
        If BS=0, 16;
96 
        If BS=1, 32;
97 
        r14 contain block size
98 
        */
99 
        l.mfspr r24,r0,SPR_ICCFGR
100 
        l.andi  r26,r24,SPR_ICCFGR_CBS
101 
        l.srli  r28,r26,7
102 
        l.ori   r30,r0,16
103 
        l.sll   r14,r30,r28
104 
 
105 
        /* Establish number of cache sets
106 
        r16 contains number of cache sets
107 
        r28 contains log(# of cache sets)
108 
        */
109 
        l.andi  r26,r24,SPR_ICCFGR_NCS
110 
        l.srli  r28,r26,3
111 
        l.ori   r30,r0,1
112 
        l.sll   r16,r30,r28
113 
 
114 
        /* Invalidate IC */
115 
        l.addi  r6,r0,0
116 
        l.sll   r5,r14,r28
117 
 
118 
.L7:
119 
        l.mtspr r0,r6,SPR_ICBIR
120 
        l.sfne  r6,r5
121 
        l.bf    .L7
122 
        l.add   r6,r6,r14
123 
 
124 
        /* Enable IC */
125 
        l.mfspr r6,r0,SPR_SR
126 
        l.ori   r6,r6,SPR_SR_ICE
127 
        l.mtspr r0,r6,SPR_SR
128 
        l.nop
129 
        l.nop
130 
        l.nop
131 
        l.nop
132 
        l.nop
133 
        l.nop
134 
        l.nop
135 
        l.nop
136 
 
137 
.L8:
138 
        /* Data cache enable */
139 
        /* Check if DC present and skip enabling otherwise */
140 
        l.mfspr r24,r0,SPR_UPR
141 
        l.andi  r26,r24,SPR_UPR_DCP
142 
        l.sfeq  r26,r0
143 
        l.bf    .L10
144 
        l.nop
145 
        /* Disable DC */
146 
        l.mfspr r6,r0,SPR_SR
147 
        l.addi  r5,r0,-1
148 
        l.xori  r5,r5,SPR_SR_DCE
149 
        l.and   r5,r6,r5
150 
        l.mtspr r0,r5,SPR_SR
151 
        /* Establish cache block size
152 
           If BS=0, 16;
153 
           If BS=1, 32;
154 
           r14 contain block size
155 
        */
156 
        l.mfspr r24,r0,SPR_DCCFGR
157 
        l.andi  r26,r24,SPR_DCCFGR_CBS
158 
        l.srli  r28,r26,7
159 
        l.ori   r30,r0,16
160 
        l.sll   r14,r30,r28
161 
        /* Establish number of cache sets
162 
           r16 contains number of cache sets
163 
           r28 contains log(# of cache sets)
164 
        */
165 
        l.andi  r26,r24,SPR_DCCFGR_NCS
166 
        l.srli  r28,r26,3
167 
        l.ori   r30,r0,1
168 
        l.sll   r16,r30,r28
169 
        /* Invalidate DC */
170 
        l.addi  r6,r0,0
171 
        l.sll   r5,r14,r28
172 
.L9:
173 
        l.mtspr r0,r6,SPR_DCBIR
174 
        l.sfne  r6,r5
175 
        l.bf    .L9
176 
        l.add   r6,r6,r14
177 
        /* Enable DC */
178 
        l.mfspr r6,r0,SPR_SR
179 
        l.ori   r6,r6,SPR_SR_DCE
180 
        l.mtspr r0,r6,SPR_SR
181 
.L10:
182 
        // Kick off test
183 
        l.jal   _main
184 
        l.nop
185 
 
186 
 
187 
 
188 
/* =================================================== [ main ] === */
189 
 
190 
        .global _main
191 
_main:
192 
        // First clear MAC
193 
        l.macrc r3
194 
        l.nop 0x2
195 
        // Load a constant into r3
196 
        l.ori   r4, r0, 0x3     // r4 = 3
197 
        l.ori   r5, r0, 0x2     // r5 = 2
198 
        l.ori   r6, r0, 0       // r6 = 0
199 
        l.ori   r7, r0, 0x7     // r7 = 7
200 
        // Test back-to-back l.mac operations
201 
        l.mac   r4, r5          // Multiply: MAC reg 6
202 
        l.mac   r4, r7          // Multiply: MAC reg 27
203 
        l.mac   r5, r5          // Multiply: MAC reg 31
204 
        l.mac   r4, r0          // Multiply: MAC reg 31
205 
        l.mac   r4, r5          // Multiply: MAC reg 37 (0x25)
206 
        l.macrc r3
207 
        l.nop 0x2
208 
        l.sfeqi r3, 0x25
209 
        l.bnf fail
210 
        l.ori r3, r0, 0x1       // Test 1 failed
211 
 
212 
        // Test back-to-back l.maci operations
213 
        l.maci  r4, 5           // Multiply: MAC reg 15
214 
        l.maci  r4, 8           // Multiply: MAC reg 39
215 
        l.maci  r5, 1           // Multiply: MAC reg 41
216 
        l.maci  r4, 0           // Multiply: MAC reg 41
217 
        l.maci  r4, 3           // Multiply: MAC reg 50 (0x32)
218 
        l.nop
219 
        l.nop
220 
        l.macrc r3
221 
        l.nop 0x2
222 
        l.sfeqi r3, 0x32
223 
        l.bnf fail
224 
        l.ori r3, r0, 0x2       // Test 2 failed
225 
 
226 
 
227 
#define NUM_MAC_LOOPS 8
228 
macloop:
229 
        l.mac   r4, r5          // Multiply: MAC reg 6
230 
        l.addi  r6, r6, 1       // Increment counter
231 
        l.sfltui r6, NUM_MAC_LOOPS
232 
        l.bf    macloop
233 
        l.nop
234 
        l.macrc r3
235 
        l.nop 0x2
236 
        l.sfeqi r3, (NUM_MAC_LOOPS*6)
237 
        l.bnf   fail
238 
        l.ori   r3, r0, 0x3     // Test 3 failed
239 
 
240 
 
241 
        l.movhi r3, 0x8000
242 
        l.ori   r3, r3, 0x000d
243 
        l.nop   0x1
244 
 
245 
fail:
246 
        l.nop 0x1
247 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.