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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-mac.S] - Blame information for rev 502

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1 356 julius 
/*
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        OR1200 MAC test
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        Very basic, testing simple instructions and multiplication,
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        accumulation values
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        Julius Baxter, julius.baxter@orsoc.se
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*/
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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// Check MAC unit is enabled before trying to run this test
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#ifndef OR1200_MAC_IMPLEMENTED
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# error
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# error No MAC unit detected. This test requires hardware MAC support
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# error
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#endif
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/* =================================================== [ exceptions ] === */
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        .section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        /* Clear status register */
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        l.ori r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Jump to program initialisation code */
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        .global _start
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        l.movhi r4, hi(_start)
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        l.ori r4, r4, lo(_start)
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        l.jr    r4
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        l.nop
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/* =================================================== [ text ] === */
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        .section .text
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/* =================================================== [ start ] === */
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        .global _start
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_start:
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        /* Instruction cache enable */
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        /* Check if IC present and skip enabling otherwise */
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        l.mfspr r24,r0,SPR_UPR
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        l.andi  r26,r24,SPR_UPR_ICP
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        l.sfeq  r26,r0
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        l.bf    .L8
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        l.nop
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        /* Disable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_ICE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        /* Establish cache block size
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        If BS=0, 16;
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        If BS=1, 32;
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        r14 contain block size
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        */
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        l.mfspr r24,r0,SPR_ICCFGR
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        l.andi  r26,r24,SPR_ICCFGR_CBS
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        l.srli  r28,r26,7
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        l.ori   r30,r0,16
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        l.sll   r14,r30,r28
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        /* Establish number of cache sets
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        r16 contains number of cache sets
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        r28 contains log(# of cache sets)
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        */
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        l.andi  r26,r24,SPR_ICCFGR_NCS
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        l.srli  r28,r26,3
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        l.ori   r30,r0,1
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        l.sll   r16,r30,r28
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        /* Invalidate IC */
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        l.addi  r6,r0,0
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        l.sll   r5,r14,r28
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.L7:
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        l.mtspr r0,r6,SPR_ICBIR
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        l.sfne  r6,r5
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        l.bf    .L7
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        l.add   r6,r6,r14
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        /* Enable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.ori   r6,r6,SPR_SR_ICE
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        l.mtspr r0,r6,SPR_SR
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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.L8:
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        /* Data cache enable */
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        /* Check if DC present and skip enabling otherwise */
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        l.mfspr r24,r0,SPR_UPR
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        l.andi  r26,r24,SPR_UPR_DCP
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        l.sfeq  r26,r0
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        l.bf    .L10
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        l.nop
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        /* Disable DC */
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        /* Establish cache block size
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           If BS=0, 16;
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           If BS=1, 32;
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           r14 contain block size
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        */
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        l.mfspr r24,r0,SPR_DCCFGR
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        l.andi  r26,r24,SPR_DCCFGR_CBS
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        l.srli  r28,r26,7
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        l.ori   r30,r0,16
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        l.sll   r14,r30,r28
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        /* Establish number of cache sets
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           r16 contains number of cache sets
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           r28 contains log(# of cache sets)
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        */
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        l.andi  r26,r24,SPR_DCCFGR_NCS
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        l.srli  r28,r26,3
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        l.ori   r30,r0,1
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        l.sll   r16,r30,r28
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        /* Invalidate DC */
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        l.addi  r6,r0,0
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        l.sll   r5,r14,r28
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.L9:
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        l.mtspr r0,r6,SPR_DCBIR
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        l.sfne  r6,r5
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        l.bf    .L9
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        l.add   r6,r6,r14
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        /* Enable DC */
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        l.mfspr r6,r0,SPR_SR
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        l.ori   r6,r6,SPR_SR_DCE
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        l.mtspr r0,r6,SPR_SR
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.L10:
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        // Kick off test
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        l.jal   _main
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        l.nop
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/* =================================================== [ main ] === */
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        .global _main
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_main:
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        // First clear MAC
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        l.macrc r3
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        l.nop 0x2
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        // Load a constant into r3
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        l.ori   r4, r0, 0x3     // r4 = 3
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        l.ori   r5, r0, 0x2     // r5 = 2
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        l.ori   r6, r0, 0       // r6 = 0
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        l.ori   r7, r0, 0x7     // r7 = 7
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        // Test back-to-back l.mac operations
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        l.mac   r4, r5          // Multiply: MAC reg 6
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        l.mac   r4, r7          // Multiply: MAC reg 27
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        l.mac   r5, r5          // Multiply: MAC reg 31
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        l.mac   r4, r0          // Multiply: MAC reg 31
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        l.mac   r4, r5          // Multiply: MAC reg 37 (0x25)
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        l.macrc r3
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        l.nop 0x2
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        l.sfeqi r3, 0x25
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        l.bnf fail
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        l.ori r3, r0, 0x1       // Test 1 failed
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        // Test back-to-back l.maci operations
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        l.maci  r4, 5           // Multiply: MAC reg 15
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        l.maci  r4, 8           // Multiply: MAC reg 39
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        l.maci  r5, 1           // Multiply: MAC reg 41
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        l.maci  r4, 0           // Multiply: MAC reg 41
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        l.maci  r4, 3           // Multiply: MAC reg 50 (0x32)
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        l.macrc r3
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        l.nop 0x2
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        l.sfeqi r3, 0x32
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        l.bnf fail
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        l.ori r3, r0, 0x2       // Test 2 failed
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#define NUM_MAC_LOOPS 8
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macloop:
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        l.mac   r4, r5          // Multiply: MAC reg 6
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        l.addi  r6, r6, 1       // Increment counter
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        l.sfltui r6, NUM_MAC_LOOPS
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        l.bf    macloop
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        l.nop
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        l.macrc r3
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        l.nop 0x2
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        l.sfeqi r3, (NUM_MAC_LOOPS*6)
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        l.bnf   fail
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        l.ori   r3, r0, 0x3     // Test 3 failed
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        l.movhi r3, 0x8000
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        l.ori   r3, r3, 0x000d
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        l.nop   0x2
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        l.ori   r3, r0, 0
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        l.nop   0x1
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fail:
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        l.nop 0x1
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