OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-maci.S] - Blame information for rev 545

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 397 julius
/*
2
        OR1200 MAC test
3
 
4
        Very basic, testing simple instructions and multiplication,
5
        accumulation values
6
 
7
        Julius Baxter, julius.baxter@orsoc.se
8
 
9
*/
10
//////////////////////////////////////////////////////////////////////
11
////                                                              ////
12
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
13
////                                                              ////
14
//// This source file may be used and distributed without         ////
15
//// restriction provided that this copyright statement is not    ////
16
//// removed from the file and that any derivative work contains  ////
17
//// the original copyright notice and the associated disclaimer. ////
18
////                                                              ////
19
//// This source file is free software; you can redistribute it   ////
20
//// and/or modify it under the terms of the GNU Lesser General   ////
21
//// Public License as published by the Free Software Foundation; ////
22
//// either version 2.1 of the License, or (at your option) any   ////
23
//// later version.                                               ////
24
////                                                              ////
25
//// This source is distributed in the hope that it will be       ////
26
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
27
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
28
//// PURPOSE.  See the GNU Lesser General Public License for more ////
29
//// details.                                                     ////
30
////                                                              ////
31
//// You should have received a copy of the GNU Lesser General    ////
32
//// Public License along with this source; if not, download it   ////
33
//// from http://www.opencores.org/lgpl.shtml                     ////
34
////                                                              ////
35
//////////////////////////////////////////////////////////////////////
36
 
37
 
38
#include "spr-defs.h"
39
#include "board.h"
40
#include "or1200-defines.h"
41
 
42
// Check MAC unit is enabled before trying to run this test
43
#ifndef OR1200_MAC_IMPLEMENTED
44
# error
45
# error No MAC unit detected. This test requires hardware MAC support
46
# error
47
#endif
48
 
49
 
50
/* =================================================== [ exceptions ] === */
51
        .section .vectors, "ax"
52
 
53
 
54
/* ---[ 0x100: RESET exception ]----------------------------------------- */
55
        .org 0x100
56
        l.movhi r0, 0
57
        /* Clear status register */
58
        l.ori r1, r0, SPR_SR_SM
59
        l.mtspr r0, r1, SPR_SR
60
        /* Clear timer  */
61
        l.mtspr r0, r0, SPR_TTMR
62
 
63
        /* Jump to program initialisation code */
64
        .global _start
65
        l.movhi r4, hi(_start)
66
        l.ori r4, r4, lo(_start)
67
        l.jr    r4
68
        l.nop
69
 
70
        .org 0x600
71
        l.nop 0x1
72
 
73
        .org 0x700
74
        l.nop 0x1
75
 
76
 
77
/* =================================================== [ text ] === */
78
        .section .text
79
 
80
/* =================================================== [ start ] === */
81
 
82
        .global _start
83
_start:
84
        // Kick off test
85
        l.jal   _main
86
        l.nop
87
 
88
 
89
 
90
/* =================================================== [ main ] === */
91
 
92
        .global _main
93
_main:
94
        // First clear MAC
95
        l.macrc r3
96
 
97
        /* Jeremy stuff. A l.maci which should not overflow */
98
        l.movhi r4,hi(0x00000002)
99
        l.ori   r4,r4,lo(0x00000002)
100
 
101
        l.mtspr r0,r0,SPR_MACHI
102
        l.mtspr r0,r0,SPR_MACLO
103
 
104
        l.maci  r4,0x0002
105
 
106
        l.mfspr r3,r0,SPR_MACHI
107
        l.nop   0x2
108
        l.nop
109
        l.mfspr r3,r0,SPR_MACLO
110
        l.nop   0x2
111
        l.nop
112
 
113
        /* Jeremy stuff. A l.maci which should overflow and be truncated. */
114
        l.movhi r4,hi(0x7fffffff)
115
        l.ori   r4,r4,lo(0x7fffffff)
116
 
117
        l.mtspr r0,r0,SPR_MACHI
118
        l.mtspr r0,r0,SPR_MACLO
119
 
120
        l.maci  r4,0x7fff
121
 
122
        l.mfspr r3,r0,SPR_MACHI
123
        l.nop   0x2
124
        l.nop
125
        l.mfspr r3,r0,SPR_MACLO
126
        l.nop   0x2
127
        l.nop
128 425 julius
        l.movhi r3, hi(0x8000000d)
129
        l.ori   r3, r3, lo(0x8000000d)
130
        l.nop   0x2
131
        l.ori   r3, r0, 0
132
        l.nop   0x1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.