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julius |
/*
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Test of return from execption behavior
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For now, just a simple test confirming that the instructions we l.rfe
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to are executed OK.
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In this test we just increment a counter and confirm this occurred.
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Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
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Register usage:
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r1: function call address
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r2: SR when function is called
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r3: test counter
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r4: temp register
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r5: temp register
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* ---[ 0xE00: TRAP exception ]----------------------------------------- */
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.org 0xe00
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/* Traps occur when we want to call a function - function address will
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be in r1, desired SR will be in r2.
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Put EPCR+4 into r9 - link register, function will return
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that way*/
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l.mfspr r9,r0,SPR_EPCR_BASE
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l.addi r9,r9,4 /* One instruction past l.trap that got us here */
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l.mtspr r0,r1,SPR_EPCR_BASE
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l.mtspr r0,r2,SPR_ESR_BASE
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l.rfe
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/* An unsupported instruction in delay slot, which should not be
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executed */
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lf.add.d r1,r2,r3
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/* =================================================== [ text ] === */
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.section .text
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/* =================================================== [ start ] === */
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.global _start
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_start:
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// Kick off test
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l.jal _main
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l.nop
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/* =================================================== [ main ] === */
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/* Call a function with l.rfe */
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#define CALL_FN_WITH_RFE(fn) \
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l.movhi r1,hi(fn) ;\
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l.ori r1,r1,lo(fn) ;\
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l.mfspr r2,r0,SPR_SR ;\
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l.trap 15
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.global _main
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_main:
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/* First test, call some functions by l.rfe'ing */
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l.movhi r3,0 /* r3 = function call counter */
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CALL_FN_WITH_RFE(function1)
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CALL_FN_WITH_RFE(function1)
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#define EXPECTED_RESULT 2
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/* Check result in r3 against the define */
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l.sfnei r3,EXPECTED_RESULT
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l.bf fail
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l.nop
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check_for_restart:
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l.mfspr r4,r0,SPR_SR
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l.andi r4,r4,SPR_SR_ICE /* is instruction cache enabled? */
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l.sfgtu r4,r0
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l.bnf restart_with_caches
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l.nop
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finish:
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l.movhi r3,0x8000
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l.ori r3,r3,0x000d
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l.nop 0x2
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l.movhi r3,0
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l.nop 0x2
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l.nop 0x1
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l.nop
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fail:
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l.movhi r3,0xbaaa
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l.ori r3,r3,0xaaad
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l.nop 0x2
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l.nop 0x1
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function1:
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l.addi r3,r3,1 /* Increment function call counter */
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l.jr r9
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l.nop 0x2 /* Report value */
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restart_with_caches:
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l.jal _cache_init
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l.nop
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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