OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-rfe.S] - Blame information for rev 545

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 535 julius
/*
2
        Test of return from execption behavior
3
 
4
        For now, just a simple test confirming that the instructions we l.rfe
5
        to are executed OK.
6
 
7
        In this test we just increment a counter and confirm this occurred.
8
 
9
        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
10
 
11
        Register usage:
12
 
13
r1:      function call address
14
r2:      SR when function is called
15
r3:      test counter
16
r4:      temp register
17
r5:      temp register
18
 
19
*/
20
//////////////////////////////////////////////////////////////////////
21
////                                                              ////
22
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
23
////                                                              ////
24
//// This source file may be used and distributed without         ////
25
//// restriction provided that this copyright statement is not    ////
26
//// removed from the file and that any derivative work contains  ////
27
//// the original copyright notice and the associated disclaimer. ////
28
////                                                              ////
29
//// This source file is free software; you can redistribute it   ////
30
//// and/or modify it under the terms of the GNU Lesser General   ////
31
//// Public License as published by the Free Software Foundation; ////
32
//// either version 2.1 of the License, or (at your option) any   ////
33
//// later version.                                               ////
34
////                                                              ////
35
//// This source is distributed in the hope that it will be       ////
36
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
37
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
38
//// PURPOSE.  See the GNU Lesser General Public License for more ////
39
//// details.                                                     ////
40
////                                                              ////
41
//// You should have received a copy of the GNU Lesser General    ////
42
//// Public License along with this source; if not, download it   ////
43
//// from http://www.opencores.org/lgpl.shtml                     ////
44
////                                                              ////
45
//////////////////////////////////////////////////////////////////////
46
 
47
#include "spr-defs.h"
48
#include "board.h"
49
#include "or1200-defines.h"
50
 
51
/* =================================================== [ exceptions ] === */
52
        .section .vectors, "ax"
53
 
54
 
55
/* ---[ 0x100: RESET exception ]----------------------------------------- */
56
        .org 0x100
57
        l.movhi r0, 0
58
        /* Clear status register */
59
        l.ori r1, r0, SPR_SR_SM
60
        l.mtspr r0, r1, SPR_SR
61
        /* Clear timer  */
62
        l.mtspr r0, r0, SPR_TTMR
63
 
64
        /* Jump to program initialisation code */
65
        .global _start
66
        l.movhi r4, hi(_start)
67
        l.ori r4, r4, lo(_start)
68
        l.jr    r4
69
        l.nop
70
 
71
/* ---[ 0xE00: TRAP exception ]----------------------------------------- */
72
        .org 0xe00
73
        /* Traps occur when we want to call a function - function address will
74
        be in r1, desired SR will be in r2.
75
        Put EPCR+4 into r9 - link register, function will return
76
        that way*/
77
        l.mfspr r9,r0,SPR_EPCR_BASE
78
        l.addi  r9,r9,4 /* One instruction past l.trap that got us here */
79
        l.mtspr r0,r1,SPR_EPCR_BASE
80
        l.mtspr r0,r2,SPR_ESR_BASE
81
        l.rfe
82
        /* An unsupported instruction in delay slot, which should not be
83
        executed */
84
        lf.add.d r1,r2,r3
85
 
86
/* =================================================== [ text ] === */
87
        .section .text
88
 
89
/* =================================================== [ start ] === */
90
 
91
        .global _start
92
_start:
93
 
94
        // Kick off test
95
        l.jal   _main
96
        l.nop
97
 
98
/* =================================================== [ main ] === */
99
 
100
/* Call a function with l.rfe */
101
#define CALL_FN_WITH_RFE(fn)            \
102
        l.movhi r1,hi(fn)               ;\
103
        l.ori   r1,r1,lo(fn)            ;\
104
        l.mfspr r2,r0,SPR_SR            ;\
105
        l.trap  15
106
 
107
        .global _main
108
_main:
109
        /* First test, call some functions by l.rfe'ing */
110
        l.movhi r3,0 /* r3 = function call counter */
111
 
112
        CALL_FN_WITH_RFE(function1)
113
        CALL_FN_WITH_RFE(function1)
114
 
115
 
116
#define EXPECTED_RESULT  2
117
        /* Check result in r3 against the define */
118
        l.sfnei r3,EXPECTED_RESULT
119
        l.bf    fail
120
        l.nop
121
 
122
check_for_restart:
123
        l.mfspr r4,r0,SPR_SR
124
        l.andi  r4,r4,SPR_SR_ICE /* is instruction cache enabled? */
125
        l.sfgtu r4,r0
126
        l.bnf   restart_with_caches
127
        l.nop
128
 
129
finish:
130
        l.movhi r3,0x8000
131
        l.ori   r3,r3,0x000d
132
        l.nop   0x2
133
        l.movhi r3,0
134
        l.nop   0x2
135
        l.nop   0x1
136
        l.nop
137
 
138
fail:
139
        l.movhi r3,0xbaaa
140
        l.ori   r3,r3,0xaaad
141
        l.nop   0x2
142
        l.nop   0x1
143
 
144
function1:
145
        l.addi  r3,r3,1 /* Increment function call counter */
146
        l.jr    r9
147
        l.nop   0x2 /* Report value */
148
 
149
restart_with_caches:
150
        l.jal   _cache_init
151
        l.nop
152
        l.movhi r4, hi(_start)
153
        l.ori r4, r4, lo(_start)
154
        l.jr    r4
155
        l.nop
156
 
157
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.