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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-tick.S] - Blame information for rev 481

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/*
 
        Tick timer interrupt test
 
        We specify our own reset and initialisation routines as we don't link
        in the usual initialisation code.
 
        Based on original or1200 tick timer test
 
        modified by
 
        Julius Baxter, julius@opencores.org
        Tadej Markovic, tadej@opencores.org
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
#include "spr-defs.h"
#include "board.h"
#define  RAM_START 0x0
 
/*      Within the test we'll use following global variables:
 
        r16 interrupt counter
        r17 current tick timer comparison counter
        r18 sanity counter
        r19 loop counter
        r20 temp value of SR reg
        r21 temp value of TTMR reg.
        r23 RAM_START
 
        r25-r31 used by int handler
 
        The test do the following:
        We set up the tick timer to trigger once and then we trigger interrupts
        incrementally on every cycle in the specified test program; on
        interrupt handler we check if data computed so far exactly matches
        precalculated values. If interrupt has returned incorreclty, we can
        detect this using assertion routine at the end.
*/
 
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global _stack
        l.movhi r1, hi(_stack)
        l.ori   r1, r1, lo(_stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* ================================================== [ tick interrupt ] === */
        .org 0x500
 
        .global _tick_handler
 
_tick_handler:
        l.addi  r31,r3,0
        # get interrupted program pc
        l.mfspr r25,r0,SPR_EPCR_BASE
 
        # calculate instruction address
        l.movhi r26,hi(_ie_start)
        l.ori   r26,r26,lo(_ie_start)
        l.addi  r3,r25,0    #print insn index
        l.nop   2
        l.sub   r25,r25,r26
        l.addi  r3,r25,0    #print insn index
        l.nop   2
 
        l.addi  r3,r31,0    # restore r3
        l.sfeqi r25, 0x00
        l.bf    _i00
        l.sfeqi r25, 0x04
        l.bf    _i04
        l.sfeqi r25, 0x08
        l.bf    _i08
        l.sfeqi r25, 0x0c
        l.bf    _i0c
        l.sfeqi r25, 0x10
        l.bf    _i10
        l.sfeqi r25, 0x14
        l.bf    _i14
        l.sfeqi r25, 0x18
        l.bf    _i18
        l.sfeqi r25, 0x1c
        l.bf    _i1c
        l.sfeqi r25, 0x20
        l.bf    _i20
        l.sfeqi r25, 0x24
        l.bf    _i24
        l.sfeqi r25, 0x28
        l.bf    _i28
        l.sfeqi r25, 0x2c
        l.bf    _i2c
        l.sfeqi r25, 0x30
        l.bf    _i30
        l.sfeqi r25, 0x34
        l.bf    _i34
        l.sfeqi r25, 0x38
        l.bf    _i38
        l.nop
 
        # value not defined
_die:
        l.nop   2             #print r3
 
        l.addi  r3,r0,0xeeee
        l.nop   2
        l.addi  r3,r0,1
        l.jal     exit
        l.nop
1:
        l.j     1b
        l.nop
 
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
.L10:
        // Kick off test
        l.jal   _main
        l.nop
 
/* ========================================================= [ main ] === */
 
        .global _main
_main:
        #
        # set tick counter to initial 3 cycles
        #
        l.addi r16,r0,0
        l.addi r17,r0,1
        l.addi r18,r0,0
        l.addi r19,r0,0
        l.addi r22,r0,0
 
        l.movhi r23,hi(RAM_START)
        l.ori   r23,r23,lo(RAM_START)
 
        #
        # unmask all ints
        #
        l.movhi r5,0xffff
        l.ori   r5,r5,0xffff
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
 
        # Set r20 to hold enable exceptions and interrupts
        l.mfspr r20,r0,SPR_SR
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
 
        # Set r21 to hold value of TTMR
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
        l.add  r21,r5,r17
 
        #
        # MAIN LOOP
        #
_main_loop:
        # reinitialize memory and registers
        l.addi  r3,r0,0xaaaa
        l.addi  r9,r0,0xbbbb
        l.sw    0(r23),r3
        l.sw    4(r23),r9
        l.sw    8(r23),r3
 
        # Reinitializes tick timer
        l.addi  r17,r17,1
        l.mtspr r0,r0,SPR_TTCR          # set TTCR
        l.mtspr r0,r21,SPR_TTMR         # set TTMR
        l.mtspr r0,r0,SPR_TTCR          # set TTCR
        l.addi  r21,r21,1
 
        # Enable exceptions and interrupts
        l.mtspr r0,r20,SPR_SR   # set SR
 
        ##### TEST CODE #####
_ie_start:
        l.movhi r3,0x1234         #00
        l.sw    0(r23),r3         #04
        l.movhi r3,hi(RAM_START)  #08
        l.lwz   r3,0(r3)          #0c
        l.movhi r3,hi(RAM_START)  #10
        l.addi  r3,r3,4           #14
        l.j     1f                #18
        l.lwz   r3,0(r3)          #1c
        l.addi  r3,r3,1           #20
1:
        l.sfeqi r3,0xdead         #24
        l.jal   2f                #28
        l.addi  r3,r0,0x5678      #2c
 
_return_addr:
2:
        l.bf    _die              #30
        l.sw    8(r23),r3         #34
_ie_end:
        l.nop                     #38
        ##### END OF TEST CODE #####
 
        # do some testing
 
        l.j     _main_loop
        l.nop
 
_i00:
        l.sfeqi r3,0xaaaa
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i04:
        l.movhi  r26,0x1234
        l.sfeq   r3,r26
        l.bnf   _die
        l.nop
        l.lwz   r26,0(r23)
        l.sfeqi r26,0xaaaa
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i08:
        l.movhi r26,0x1234
        l.sfeq  r3,r26
        l.bnf   _die
        l.nop
        l.lwz   r27,0(r23)
        l.sfeq  r27,r26
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i0c:
        l.sfeq  r3,r23
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i10:
        l.movhi r26,0x1234
        l.sfeq  r26,r3
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i14:
        l.sfeq  r3,r23
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i18:
        l.addi  r26,r23,4
        l.sfeq  r3,r26
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i1c:
        l.j     _die
        l.nop
_i20:
        l.j     _die
        l.nop
_i24:
        l.mfspr r26,r0,SPR_ESR_BASE
        l.addi  r30,r3,0
        l.addi  r3,r26,0
        l.nop   2
        l.addi  r3,r30,0
        l.andi  r26,r26,SPR_SR_F
        l.sfeq  r26,r0
        l.bf   _die
        l.nop
        l.sfeqi  r3,0xbbbb
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i28:
        l.mfspr r26,r0,SPR_ESR_BASE
        l.addi  r30,r3,0
        l.addi  r3,r26,0
        l.nop   2
        l.addi  r3,r30,0
        l.andi  r26,r26,SPR_SR_F
        l.sfeq  r26,r0
        l.bnf    _die
        l.nop
        l.sfeqi  r22,1
        l.bf     _resume
        l.addi   r22,r0,1
        l.sfeqi  r9,0xbbbb
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i2c:
        l.movhi  r26,hi(_return_addr)
        l.ori    r26,r26,lo(_return_addr)
        l.sfeq   r9,r26
        l.bnf   _die
        l.nop
        l.sfeqi  r3,0xbbbb
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i30:
        l.sfeqi  r3,0x5678
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i34:
        l.sfeqi  r3,0x5678
        l.bnf   _die
        l.nop
        l.lwz    r26,8(r23)
        l.sfeqi  r26,0xaaaa
        l.bnf   _die
        l.nop
        l.j     _resume
        l.nop
_i38:
        l.lwz    r26,8(r23)
        l.sfeqi  r26,0x5678
        l.bnf   _die
        l.nop
        #
        # mark finished ok
        #
        l.movhi r3,hi(0xdeaddead)
        l.ori   r3,r3,lo(0xdeaddead)
        l.nop   2
        l.movhi r3,hi(0x8000000d)
        l.ori   r3,r3,lo(0x8000000d)
        l.nop   2
        l.addi  r3,r0,0
 
        l.jal     exit
        l.nop
_ok:
        l.j     _ok
        l.nop
 
_resume:
        l.mfspr  r27,r0,SPR_ESR_BASE
        l.addi   r26,r0,SPR_SR_TEE
        l.addi   r28,r0,-1
        l.xor    r26,r26,r28
        l.and    r26,r26,r27
        l.mtspr  r0,r26,SPR_ESR_BASE
 
        l.rfe
        l.addi    r3,r3,5         # should not be executed

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-tick.S] - Blame information for rev 481

Line No.	Rev	Author	Line
1	349	julius	`/*`
2
3			`Tick timer interrupt test`
4
5			`We specify our own reset and initialisation routines as we don't link`
6			`in the usual initialisation code.`
7
8			`Based on original or1200 tick timer test`
9
10			`modified by`
11
12			`Julius Baxter, julius@opencores.org`
13			`Tadej Markovic, tadej@opencores.org`
14
15			`*/`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43
44			`#include "spr-defs.h"`
45			`#include "board.h"`
46	408	julius	`#define RAM_START 0x0`
47	349	julius
48			`/* Within the test we'll use following global variables:`
49
50			`r16 interrupt counter`
51			`r17 current tick timer comparison counter`
52			`r18 sanity counter`
53			`r19 loop counter`
54			`r20 temp value of SR reg`
55			`r21 temp value of TTMR reg.`
56			`r23 RAM_START`
57
58			`r25-r31 used by int handler`
59
60			`The test do the following:`
61			`We set up the tick timer to trigger once and then we trigger interrupts`
62			`incrementally on every cycle in the specified test program; on`
63			`interrupt handler we check if data computed so far exactly matches`
64			`precalculated values. If interrupt has returned incorreclty, we can`
65			`detect this using assertion routine at the end.`
66			`*/`
67
68
69
70			`/* =================================================== [ exceptions ] === */`
71			`.section .vectors, "ax"`
72
73
74			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
75			`.org 0x100`
76			`l.movhi r0, 0`
77			`/* Clear status register */`
78			`l.ori r1, r0, SPR_SR_SM`
79			`l.mtspr r0, r1, SPR_SR`
80			`/* Clear timer */`
81			`l.mtspr r0, r0, SPR_TTMR`
82			`/* Init the stack */`
83			`.global _stack`
84			`l.movhi r1, hi(_stack)`
85			`l.ori r1, r1, lo(_stack)`
86			`l.addi r2, r0, -3`
87			`l.and r1, r1, r2`
88			`/* Jump to program initialisation code */`
89			`.global _start`
90			`l.movhi r4, hi(_start)`
91			`l.ori r4, r4, lo(_start)`
92			`l.jr r4`
93			`l.nop`
94
95
96			`/* ================================================== [ tick interrupt ] === */`
97			`.org 0x500`
98
99			`.global _tick_handler`
100
101			`_tick_handler:`
102			`l.addi r31,r3,0`
103			`# get interrupted program pc`
104			`l.mfspr r25,r0,SPR_EPCR_BASE`
105
106			`# calculate instruction address`
107			`l.movhi r26,hi(_ie_start)`
108			`l.ori r26,r26,lo(_ie_start)`
109			`l.addi r3,r25,0 #print insn index`
110			`l.nop 2`
111			`l.sub r25,r25,r26`
112			`l.addi r3,r25,0 #print insn index`
113			`l.nop 2`
114
115			`l.addi r3,r31,0 # restore r3`
116			`l.sfeqi r25, 0x00`
117			`l.bf _i00`
118			`l.sfeqi r25, 0x04`
119			`l.bf _i04`
120			`l.sfeqi r25, 0x08`
121			`l.bf _i08`
122			`l.sfeqi r25, 0x0c`
123			`l.bf _i0c`
124			`l.sfeqi r25, 0x10`
125			`l.bf _i10`
126			`l.sfeqi r25, 0x14`
127			`l.bf _i14`
128			`l.sfeqi r25, 0x18`
129			`l.bf _i18`
130			`l.sfeqi r25, 0x1c`
131			`l.bf _i1c`
132			`l.sfeqi r25, 0x20`
133			`l.bf _i20`
134			`l.sfeqi r25, 0x24`
135			`l.bf _i24`
136			`l.sfeqi r25, 0x28`
137			`l.bf _i28`
138			`l.sfeqi r25, 0x2c`
139			`l.bf _i2c`
140			`l.sfeqi r25, 0x30`
141			`l.bf _i30`
142			`l.sfeqi r25, 0x34`
143			`l.bf _i34`
144			`l.sfeqi r25, 0x38`
145			`l.bf _i38`
146			`l.nop`
147
148			`# value not defined`
149			`_die:`
150			`l.nop 2 #print r3`
151
152			`l.addi r3,r0,0xeeee`
153			`l.nop 2`
154			`l.addi r3,r0,1`
155	373	julius	`l.jal exit`
156	349	julius	`l.nop`
157			`1:`
158			`l.j 1b`
159			`l.nop`
160
161
162			`/* =================================================== [ text section ] === */`
163			`.section .text`
164
165			`/* =================================================== [ start ] === */`
166
167			`.global _start`
168			`_start:`
169
170			`/* Instruction cache enable */`
171			`/* Check if IC present and skip enabling otherwise */`
172			`l.mfspr r24,r0,SPR_UPR`
173			`l.andi r26,r24,SPR_UPR_ICP`
174			`l.sfeq r26,r0`
175			`l.bf .L8`
176			`l.nop`
177
178			`/* Disable IC */`
179			`l.mfspr r6,r0,SPR_SR`
180			`l.addi r5,r0,-1`
181			`l.xori r5,r5,SPR_SR_ICE`
182			`l.and r5,r6,r5`
183			`l.mtspr r0,r5,SPR_SR`
184
185			`/* Establish cache block size`
186			`If BS=0, 16;`
187			`If BS=1, 32;`
188			`r14 contain block size`
189			`*/`
190			`l.mfspr r24,r0,SPR_ICCFGR`
191			`l.andi r26,r24,SPR_ICCFGR_CBS`
192			`l.srli r28,r26,7`
193			`l.ori r30,r0,16`
194			`l.sll r14,r30,r28`
195
196			`/* Establish number of cache sets`
197			`r16 contains number of cache sets`
198			`r28 contains log(# of cache sets)`
199			`*/`
200			`l.andi r26,r24,SPR_ICCFGR_NCS`
201			`l.srli r28,r26,3`
202			`l.ori r30,r0,1`
203			`l.sll r16,r30,r28`
204
205			`/* Invalidate IC */`
206			`l.addi r6,r0,0`
207			`l.sll r5,r14,r28`
208
209			`.L7:`
210			`l.mtspr r0,r6,SPR_ICBIR`
211			`l.sfne r6,r5`
212			`l.bf .L7`
213			`l.add r6,r6,r14`
214
215			`/* Enable IC */`
216			`l.mfspr r6,r0,SPR_SR`
217			`l.ori r6,r6,SPR_SR_ICE`
218			`l.mtspr r0,r6,SPR_SR`
219			`l.nop`
220			`l.nop`
221			`l.nop`
222			`l.nop`
223			`l.nop`
224			`l.nop`
225			`l.nop`
226			`l.nop`
227
228			`.L8:`
229			`/* Data cache enable */`
230			`/* Check if DC present and skip enabling otherwise */`
231			`l.mfspr r24,r0,SPR_UPR`
232			`l.andi r26,r24,SPR_UPR_DCP`
233			`l.sfeq r26,r0`
234			`l.bf .L10`
235			`l.nop`
236			`/* Disable DC */`
237			`l.mfspr r6,r0,SPR_SR`
238			`l.addi r5,r0,-1`
239			`l.xori r5,r5,SPR_SR_DCE`
240			`l.and r5,r6,r5`
241			`l.mtspr r0,r5,SPR_SR`
242			`/* Establish cache block size`
243			`If BS=0, 16;`
244			`If BS=1, 32;`
245			`r14 contain block size`
246			`*/`
247			`l.mfspr r24,r0,SPR_DCCFGR`
248			`l.andi r26,r24,SPR_DCCFGR_CBS`
249			`l.srli r28,r26,7`
250			`l.ori r30,r0,16`
251			`l.sll r14,r30,r28`
252			`/* Establish number of cache sets`
253			`r16 contains number of cache sets`
254			`r28 contains log(# of cache sets)`
255			`*/`
256			`l.andi r26,r24,SPR_DCCFGR_NCS`
257			`l.srli r28,r26,3`
258			`l.ori r30,r0,1`
259			`l.sll r16,r30,r28`
260			`/* Invalidate DC */`
261			`l.addi r6,r0,0`
262			`l.sll r5,r14,r28`
263			`.L9:`
264			`l.mtspr r0,r6,SPR_DCBIR`
265			`l.sfne r6,r5`
266			`l.bf .L9`
267			`l.add r6,r6,r14`
268			`/* Enable DC */`
269			`l.mfspr r6,r0,SPR_SR`
270			`l.ori r6,r6,SPR_SR_DCE`
271			`l.mtspr r0,r6,SPR_SR`
272			`.L10:`
273			`// Kick off test`
274			`l.jal _main`
275			`l.nop`
276
277			`/* ========================================================= [ main ] === */`
278
279			`.global _main`
280			`_main:`
281			`#`
282			`# set tick counter to initial 3 cycles`
283			`#`
284			`l.addi r16,r0,0`
285			`l.addi r17,r0,1`
286			`l.addi r18,r0,0`
287			`l.addi r19,r0,0`
288			`l.addi r22,r0,0`
289
290			`l.movhi r23,hi(RAM_START)`
291			`l.ori r23,r23,lo(RAM_START)`
292
293			`#`
294			`# unmask all ints`
295			`#`
296			`l.movhi r5,0xffff`
297			`l.ori r5,r5,0xffff`
298			`l.mtspr r0,r5,SPR_PICMR # set PICMR`
299
300			`# Set r20 to hold enable exceptions and interrupts`
301			`l.mfspr r20,r0,SPR_SR`
302			`l.ori r20,r20,SPR_SR_SM\|SPR_SR_TEE\|SPR_SR_F`
303
304			`# Set r21 to hold value of TTMR`
305			`l.movhi r5,hi(SPR_TTMR_SR \| SPR_TTMR_IE)`
306			`l.add r21,r5,r17`
307
308			`#`
309			`# MAIN LOOP`
310			`#`
311			`_main_loop:`
312			`# reinitialize memory and registers`
313			`l.addi r3,r0,0xaaaa`
314			`l.addi r9,r0,0xbbbb`
315			`l.sw 0(r23),r3`
316			`l.sw 4(r23),r9`
317			`l.sw 8(r23),r3`
318
319			`# Reinitializes tick timer`
320			`l.addi r17,r17,1`
321			`l.mtspr r0,r0,SPR_TTCR # set TTCR`
322			`l.mtspr r0,r21,SPR_TTMR # set TTMR`
323			`l.mtspr r0,r0,SPR_TTCR # set TTCR`
324			`l.addi r21,r21,1`
325
326			`# Enable exceptions and interrupts`
327			`l.mtspr r0,r20,SPR_SR # set SR`
328
329			`##### TEST CODE #####`
330			`_ie_start:`
331			`l.movhi r3,0x1234 #00`
332			`l.sw 0(r23),r3 #04`
333			`l.movhi r3,hi(RAM_START) #08`
334			`l.lwz r3,0(r3) #0c`
335			`l.movhi r3,hi(RAM_START) #10`
336			`l.addi r3,r3,4 #14`
337			`l.j 1f #18`
338			`l.lwz r3,0(r3) #1c`
339			`l.addi r3,r3,1 #20`
340			`1:`
341			`l.sfeqi r3,0xdead #24`
342			`l.jal 2f #28`
343			`l.addi r3,r0,0x5678 #2c`
344
345			`_return_addr:`
346			`2:`
347			`l.bf _die #30`
348			`l.sw 8(r23),r3 #34`
349			`_ie_end:`
350			`l.nop #38`
351			`##### END OF TEST CODE #####`
352
353			`# do some testing`
354
355			`l.j _main_loop`
356			`l.nop`
357
358			`_i00:`
359			`l.sfeqi r3,0xaaaa`
360			`l.bnf _die`
361			`l.nop`
362			`l.j _resume`
363			`l.nop`
364			`_i04:`
365			`l.movhi r26,0x1234`
366			`l.sfeq r3,r26`
367			`l.bnf _die`
368			`l.nop`
369			`l.lwz r26,0(r23)`
370			`l.sfeqi r26,0xaaaa`
371			`l.bnf _die`
372			`l.nop`
373			`l.j _resume`
374			`l.nop`
375			`_i08:`
376			`l.movhi r26,0x1234`
377			`l.sfeq r3,r26`
378			`l.bnf _die`
379			`l.nop`
380			`l.lwz r27,0(r23)`
381			`l.sfeq r27,r26`
382			`l.bnf _die`
383			`l.nop`
384			`l.j _resume`
385			`l.nop`
386			`_i0c:`
387			`l.sfeq r3,r23`
388			`l.bnf _die`
389			`l.nop`
390			`l.j _resume`
391			`l.nop`
392			`_i10:`
393			`l.movhi r26,0x1234`
394			`l.sfeq r26,r3`
395			`l.bnf _die`
396			`l.nop`
397			`l.j _resume`
398			`l.nop`
399			`_i14:`
400			`l.sfeq r3,r23`
401			`l.bnf _die`
402			`l.nop`
403			`l.j _resume`
404			`l.nop`
405			`_i18:`
406			`l.addi r26,r23,4`
407			`l.sfeq r3,r26`
408			`l.bnf _die`
409			`l.nop`
410			`l.j _resume`
411			`l.nop`
412			`_i1c:`
413			`l.j _die`
414			`l.nop`
415			`_i20:`
416			`l.j _die`
417			`l.nop`
418			`_i24:`
419			`l.mfspr r26,r0,SPR_ESR_BASE`
420			`l.addi r30,r3,0`
421			`l.addi r3,r26,0`
422			`l.nop 2`
423			`l.addi r3,r30,0`
424			`l.andi r26,r26,SPR_SR_F`
425			`l.sfeq r26,r0`
426			`l.bf _die`
427			`l.nop`
428			`l.sfeqi r3,0xbbbb`
429			`l.bnf _die`
430			`l.nop`
431			`l.j _resume`
432			`l.nop`
433			`_i28:`
434			`l.mfspr r26,r0,SPR_ESR_BASE`
435			`l.addi r30,r3,0`
436			`l.addi r3,r26,0`
437			`l.nop 2`
438			`l.addi r3,r30,0`
439			`l.andi r26,r26,SPR_SR_F`
440			`l.sfeq r26,r0`
441			`l.bnf _die`
442			`l.nop`
443			`l.sfeqi r22,1`
444			`l.bf _resume`
445			`l.addi r22,r0,1`
446			`l.sfeqi r9,0xbbbb`
447			`l.bnf _die`
448			`l.nop`
449			`l.j _resume`
450			`l.nop`
451			`_i2c:`
452			`l.movhi r26,hi(_return_addr)`
453			`l.ori r26,r26,lo(_return_addr)`
454			`l.sfeq r9,r26`
455			`l.bnf _die`
456			`l.nop`
457			`l.sfeqi r3,0xbbbb`
458			`l.bnf _die`
459			`l.nop`
460			`l.j _resume`
461			`l.nop`
462			`_i30:`
463			`l.sfeqi r3,0x5678`
464			`l.bnf _die`
465			`l.nop`
466			`l.j _resume`
467			`l.nop`
468			`_i34:`
469			`l.sfeqi r3,0x5678`
470			`l.bnf _die`
471			`l.nop`
472			`l.lwz r26,8(r23)`
473			`l.sfeqi r26,0xaaaa`
474			`l.bnf _die`
475			`l.nop`
476			`l.j _resume`
477			`l.nop`
478			`_i38:`
479			`l.lwz r26,8(r23)`
480			`l.sfeqi r26,0x5678`
481			`l.bnf _die`
482			`l.nop`
483			`#`
484			`# mark finished ok`
485			`#`
486			`l.movhi r3,hi(0xdeaddead)`
487			`l.ori r3,r3,lo(0xdeaddead)`
488			`l.nop 2`
489			`l.movhi r3,hi(0x8000000d)`
490			`l.ori r3,r3,lo(0x8000000d)`
491			`l.nop 2`
492			`l.addi r3,r0,0`
493
494	373	julius	`l.jal exit`
495	349	julius	`l.nop`
496			`_ok:`
497			`l.j _ok`
498			`l.nop`
499
500			`_resume:`
501			`l.mfspr r27,r0,SPR_ESR_BASE`
502			`l.addi r26,r0,SPR_SR_TEE`
503			`l.addi r28,r0,-1`
504			`l.xor r26,r26,r28`
505			`l.and r26,r26,r27`
506			`l.mtspr r0,r26,SPR_ESR_BASE`
507
508			`l.rfe`
509			`l.addi r3,r3,5 # should not be executed`