URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ticksyscall.S] - Blame information for rev 671

Details | Compare with Previous | View Log


#include "spr-defs.h"
#include "board.h"
 
/*
 
        Tick timer and system call simultaneous interrupt test
 
        Within the test we'll use following global variables:
 
        r15 syscall interrupt counter
        r16 syscall function counter
        r17 timer interrupt counter
 
 
        The test do the following:
        Setup tick interrupts to occur regularly, and then do a bunch of l.sys
        systems calls, checking that they all occur OK
 
        Note: if this test appears to continue without counting, it's most
        likely due to a tick counter value that's too small (processor is
        executing too slowly, due to lack of cache or similar) and always
        interrupting before execution can continue. Try increasing the
        TICK_COUNTER_VALUE #define to give the processor time to continue.
 
        Julius Baxter, julius@opencores.org
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
#define TICK_COUNTER_VALUE 16
 
 
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global _stack
        l.movhi r1, hi(_stack)
        l.ori   r1, r1, lo(_stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
 
/* =================================================== [ tick interrupt ] === */
        .org 0x500
        .global _tick_handler
_tick_handler:
        l.addi r17, r17, 1
# Set r7 to hold value of TTMR, one-shot mode/single run (SR)
        l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
        l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
        l.add  r7,r5,r6
        /* Report values , 0x00000500 == tick timer report*/
        l.ori r3, r0, 0x0500
        l.nop 2
        l.or r3, r0, r17
        l.nop 2
# Init the tick timer
        l.mtspr r0,r0,SPR_TTCR          # clear TTCR
        l.mtspr r0,r7,SPR_TTMR          # set TTMR
        l.rfe
 
/* ========================================================= [ syscall ] === */
        .org 0xC00
        .extern _syscall_function
        .global _syscall_handler
_syscall_handler:
        l.addi r15, r15, 1
        l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */
        l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/
        /* Unset IEE and TEE bits of SR */
        l.ori r4, r0, SPR_SR_IEE|SPR_SR_TEE
        l.ori r5, r0, 0xffff
        l.xor r5, r5, r4
        l.and r5, r7, r5 /* New SR without interrupt bits set */
        l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */
        /* Report values , 0x00000c00 == tick timer report*/
        l.ori r3, r0, 0x0c00
        l.nop 2
        /* Get syscall number */
        l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */
        l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */
        l.nop 2
        l.movhi r4, hi(_syscall_function)
        l.ori r4, r4, lo(_syscall_function)
        l.mtspr r0, r4, SPR_EPCR_BASE
        l.rfe
 
 
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
.L10:
 
        // Kick off test
        l.jal   _main
        l.nop
 
/* =================================================== [ main ] === */
.global _main
_main:
        l.movhi r15, 0
        l.movhi r16, 0
        l.movhi r17, 0
 
        #
        # unmask all ints
        #
        l.movhi r5,0xffff
        l.ori   r5,r5,0xffff
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
 
        # Set r20 to hold enable exceptions and interrupts
        l.mfspr r20,r0,SPR_SR
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE
 
        # Enable exceptions and interrupts
        l.mtspr r0,r20,SPR_SR   # set SR
 
        # Set r7 to hold value of TTMR, one-shot mode/single run (SR)
        l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
        l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
        l.add  r7,r5,r6
 
        # Init the tick timer
        l.mtspr r0,r0,SPR_TTCR          # clear TTCR
        l.mtspr r0,r7,SPR_TTMR          # set TTMR
 
_wait_loop:
        l.sfeqi r17, 0x10
        l.bnf _wait_loop
        l.nop
 
        /* Timer is working, let's start with some syscalls */
        /* These should occur before tick timer's cycle is up */
        l.nop
        l.sys 0x1
        l.nop
        l.sys 0x2
        l.nop
        l.sys 0x3
        l.nop
        l.sys 0x4
        l.nop
        l.sys 0x5
        l.nop
        l.sfnei r16, 0xf /* Should equal 15, 0xf */
        l.bf _fail
        l.nop
        /* Continue, hopefuly now intercept tick timer cycles */
        l.nop
        l.nop
        l.sys 0x6
        l.nop
        l.nop
        l.nop
        l.nop
        l.sys 0x7
        l.nop
        l.nop
        l.sys 0x8
        l.nop
        l.nop
        l.sys 0x9
        l.nop
        l.nop
        l.sys 0xa
        l.nop
        l.nop
        l.nop
        l.sys 0xb
        l.nop
        l.nop
        l.nop
        l.nop
        l.sys 0xc
        l.nop
        l.nop
        l.sys 0xd
        l.nop
        l.nop
        l.sys 0xe
        l.nop
        l.nop
        l.sys 0xf
        l.nop
        /* Now turn off tick timer */
        l.mtspr r0,r0,SPR_TTMR          # clear TTMR
        l.sfnei r16, 0x78 /* Should equal 120, 0x78 */
        l.bf _fail
        l.nop
        l.movhi r3, hi(0x8000000d)
        l.ori r3, r3, lo(0x8000000d)
        l.nop 2
        l.ori r3, r0, 0
        l.nop 1
 
_fail:
        l.movhi r3, hi(0xbaaaaaad)
        l.ori r3, r3, lo(0xbaaaaaad)
        l.nop 1
 
        .global _syscall_function
_syscall_function:
        /* r7 and r8 hold actual real ESR and EPCR, respectively */
        /* We'll restore them now */
        l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */
        l.mtspr r0, r8, SPR_EPCR_BASE
        l.add r16, r16, r3 /* Add syscall number to our counter */
        l.movhi r4, hi(0x00400000) /* 4MB mark of memory */
        /* Ensure memory access OK */
        l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */
        l.add r4, r4, r3 /* Access this offset from 4MB mark */
        l.sw 0(r4), r16 /* Do a write to memory */
        l.lwz r16, 0(r4) /* Do a read from memory */
        /* Report running value of syscall counter */
        l.or r3, r0, r16
        l.nop 2
        l.rfe /* Now continue from where we had the l.sys */
 

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ticksyscall.S] - Blame information for rev 671

Line No.	Rev	Author	Line
1	349	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`/*`
5
6			`Tick timer and system call simultaneous interrupt test`
7
8			`Within the test we'll use following global variables:`
9
10			`r15 syscall interrupt counter`
11			`r16 syscall function counter`
12			`r17 timer interrupt counter`
13
14
15			`The test do the following:`
16			`Setup tick interrupts to occur regularly, and then do a bunch of l.sys`
17			`systems calls, checking that they all occur OK`
18
19	477	julius	`Note: if this test appears to continue without counting, it's most`
20			`likely due to a tick counter value that's too small (processor is`
21			`executing too slowly, due to lack of cache or similar) and always`
22			`interrupting before execution can continue. Try increasing the`
23			`TICK_COUNTER_VALUE #define to give the processor time to continue.`
24
25	349	julius	`Julius Baxter, julius@opencores.org`
26			`*/`
27			`//////////////////////////////////////////////////////////////////////`
28			`//// ////`
29			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
30			`//// ////`
31			`//// This source file may be used and distributed without ////`
32			`//// restriction provided that this copyright statement is not ////`
33			`//// removed from the file and that any derivative work contains ////`
34			`//// the original copyright notice and the associated disclaimer. ////`
35			`//// ////`
36			`//// This source file is free software; you can redistribute it ////`
37			`//// and/or modify it under the terms of the GNU Lesser General ////`
38			`//// Public License as published by the Free Software Foundation; ////`
39			`//// either version 2.1 of the License, or (at your option) any ////`
40			`//// later version. ////`
41			`//// ////`
42			`//// This source is distributed in the hope that it will be ////`
43			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
44			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
45			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
46			`//// details. ////`
47			`//// ////`
48			`//// You should have received a copy of the GNU Lesser General ////`
49			`//// Public License along with this source; if not, download it ////`
50			`//// from http://www.opencores.org/lgpl.shtml ////`
51			`//// ////`
52			`//////////////////////////////////////////////////////////////////////`
53
54
55	477	julius	`#define TICK_COUNTER_VALUE 16`
56	349	julius
57
58	477	julius
59	349	julius	`/* =================================================== [ exceptions ] === */`
60			`.section .vectors, "ax"`
61
62
63			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
64			`.org 0x100`
65			`l.movhi r0, 0`
66			`/* Clear status register */`
67			`l.ori r1, r0, SPR_SR_SM`
68			`l.mtspr r0, r1, SPR_SR`
69			`/* Clear timer */`
70			`l.mtspr r0, r0, SPR_TTMR`
71			`/* Init the stack */`
72			`.global _stack`
73			`l.movhi r1, hi(_stack)`
74			`l.ori r1, r1, lo(_stack)`
75			`l.addi r2, r0, -3`
76			`l.and r1, r1, r2`
77			`/* Jump to program initialisation code */`
78			`.global _start`
79			`l.movhi r4, hi(_start)`
80			`l.ori r4, r4, lo(_start)`
81			`l.jr r4`
82			`l.nop`
83
84
85			`/* =================================================== [ tick interrupt ] === */`
86			`.org 0x500`
87			`.global _tick_handler`
88			`_tick_handler:`
89			`l.addi r17, r17, 1`
90			`# Set r7 to hold value of TTMR, one-shot mode/single run (SR)`
91			`l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */`
92			`l.movhi r6,hi(SPR_TTMR_SR \| SPR_TTMR_IE)`
93			`l.add r7,r5,r6`
94			`/* Report values , 0x00000500 == tick timer report*/`
95			`l.ori r3, r0, 0x0500`
96			`l.nop 2`
97			`l.or r3, r0, r17`
98			`l.nop 2`
99			`# Init the tick timer`
100			`l.mtspr r0,r0,SPR_TTCR # clear TTCR`
101			`l.mtspr r0,r7,SPR_TTMR # set TTMR`
102			`l.rfe`
103
104			`/* ========================================================= [ syscall ] === */`
105			`.org 0xC00`
106			`.extern _syscall_function`
107			`.global _syscall_handler`
108			`_syscall_handler:`
109			`l.addi r15, r15, 1`
110			`l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */`
111			`l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/`
112			`/* Unset IEE and TEE bits of SR */`
113			`l.ori r4, r0, SPR_SR_IEE\|SPR_SR_TEE`
114			`l.ori r5, r0, 0xffff`
115			`l.xor r5, r5, r4`
116			`l.and r5, r7, r5 /* New SR without interrupt bits set */`
117			`l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */`
118			`/* Report values , 0x00000c00 == tick timer report*/`
119			`l.ori r3, r0, 0x0c00`
120			`l.nop 2`
121			`/* Get syscall number */`
122			`l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */`
123			`l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */`
124			`l.nop 2`
125			`l.movhi r4, hi(_syscall_function)`
126			`l.ori r4, r4, lo(_syscall_function)`
127			`l.mtspr r0, r4, SPR_EPCR_BASE`
128			`l.rfe`
129
130
131
132			`/* =================================================== [ text section ] === */`
133			`.section .text`
134
135			`/* =================================================== [ start ] === */`
136
137			`.global _start`
138			`_start:`
139
140			`/* Instruction cache enable */`
141			`/* Check if IC present and skip enabling otherwise */`
142			`l.mfspr r24,r0,SPR_UPR`
143			`l.andi r26,r24,SPR_UPR_ICP`
144			`l.sfeq r26,r0`
145			`l.bf .L8`
146			`l.nop`
147
148			`/* Disable IC */`
149			`l.mfspr r6,r0,SPR_SR`
150			`l.addi r5,r0,-1`
151			`l.xori r5,r5,SPR_SR_ICE`
152			`l.and r5,r6,r5`
153			`l.mtspr r0,r5,SPR_SR`
154
155			`/* Establish cache block size`
156			`If BS=0, 16;`
157			`If BS=1, 32;`
158			`r14 contain block size`
159			`*/`
160			`l.mfspr r24,r0,SPR_ICCFGR`
161			`l.andi r26,r24,SPR_ICCFGR_CBS`
162			`l.srli r28,r26,7`
163			`l.ori r30,r0,16`
164			`l.sll r14,r30,r28`
165
166			`/* Establish number of cache sets`
167			`r16 contains number of cache sets`
168			`r28 contains log(# of cache sets)`
169			`*/`
170			`l.andi r26,r24,SPR_ICCFGR_NCS`
171			`l.srli r28,r26,3`
172			`l.ori r30,r0,1`
173			`l.sll r16,r30,r28`
174
175			`/* Invalidate IC */`
176			`l.addi r6,r0,0`
177			`l.sll r5,r14,r28`
178
179			`.L7:`
180			`l.mtspr r0,r6,SPR_ICBIR`
181			`l.sfne r6,r5`
182			`l.bf .L7`
183			`l.add r6,r6,r14`
184
185			`/* Enable IC */`
186			`l.mfspr r6,r0,SPR_SR`
187			`l.ori r6,r6,SPR_SR_ICE`
188			`l.mtspr r0,r6,SPR_SR`
189			`l.nop`
190			`l.nop`
191			`l.nop`
192			`l.nop`
193			`l.nop`
194			`l.nop`
195			`l.nop`
196			`l.nop`
197
198			`.L8:`
199			`/* Data cache enable */`
200			`/* Check if DC present and skip enabling otherwise */`
201			`l.mfspr r24,r0,SPR_UPR`
202			`l.andi r26,r24,SPR_UPR_DCP`
203			`l.sfeq r26,r0`
204			`l.bf .L10`
205			`l.nop`
206			`/* Disable DC */`
207			`l.mfspr r6,r0,SPR_SR`
208			`l.addi r5,r0,-1`
209			`l.xori r5,r5,SPR_SR_DCE`
210			`l.and r5,r6,r5`
211			`l.mtspr r0,r5,SPR_SR`
212			`/* Establish cache block size`
213			`If BS=0, 16;`
214			`If BS=1, 32;`
215			`r14 contain block size`
216			`*/`
217			`l.mfspr r24,r0,SPR_DCCFGR`
218			`l.andi r26,r24,SPR_DCCFGR_CBS`
219			`l.srli r28,r26,7`
220			`l.ori r30,r0,16`
221			`l.sll r14,r30,r28`
222			`/* Establish number of cache sets`
223			`r16 contains number of cache sets`
224			`r28 contains log(# of cache sets)`
225			`*/`
226			`l.andi r26,r24,SPR_DCCFGR_NCS`
227			`l.srli r28,r26,3`
228			`l.ori r30,r0,1`
229			`l.sll r16,r30,r28`
230			`/* Invalidate DC */`
231			`l.addi r6,r0,0`
232			`l.sll r5,r14,r28`
233			`.L9:`
234			`l.mtspr r0,r6,SPR_DCBIR`
235			`l.sfne r6,r5`
236			`l.bf .L9`
237			`l.add r6,r6,r14`
238			`/* Enable DC */`
239			`l.mfspr r6,r0,SPR_SR`
240			`l.ori r6,r6,SPR_SR_DCE`
241			`l.mtspr r0,r6,SPR_SR`
242			`.L10:`
243
244			`// Kick off test`
245			`l.jal _main`
246			`l.nop`
247
248			`/* =================================================== [ main ] === */`
249			`.global _main`
250			`_main:`
251			`l.movhi r15, 0`
252			`l.movhi r16, 0`
253			`l.movhi r17, 0`
254
255			`#`
256			`# unmask all ints`
257			`#`
258			`l.movhi r5,0xffff`
259			`l.ori r5,r5,0xffff`
260			`l.mtspr r0,r5,SPR_PICMR # set PICMR`
261
262			`# Set r20 to hold enable exceptions and interrupts`
263			`l.mfspr r20,r0,SPR_SR`
264			`l.ori r20,r20,SPR_SR_SM\|SPR_SR_TEE`
265
266			`# Enable exceptions and interrupts`
267			`l.mtspr r0,r20,SPR_SR # set SR`
268
269			`# Set r7 to hold value of TTMR, one-shot mode/single run (SR)`
270			`l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */`
271			`l.movhi r6,hi(SPR_TTMR_SR \| SPR_TTMR_IE)`
272			`l.add r7,r5,r6`
273
274			`# Init the tick timer`
275			`l.mtspr r0,r0,SPR_TTCR # clear TTCR`
276			`l.mtspr r0,r7,SPR_TTMR # set TTMR`
277
278			`_wait_loop:`
279			`l.sfeqi r17, 0x10`
280			`l.bnf _wait_loop`
281			`l.nop`
282
283			`/* Timer is working, let's start with some syscalls */`
284			`/* These should occur before tick timer's cycle is up */`
285			`l.nop`
286			`l.sys 0x1`
287			`l.nop`
288			`l.sys 0x2`
289			`l.nop`
290			`l.sys 0x3`
291			`l.nop`
292			`l.sys 0x4`
293			`l.nop`
294			`l.sys 0x5`
295			`l.nop`
296			`l.sfnei r16, 0xf /* Should equal 15, 0xf */`
297			`l.bf _fail`
298			`l.nop`
299			`/* Continue, hopefuly now intercept tick timer cycles */`
300			`l.nop`
301			`l.nop`
302			`l.sys 0x6`
303			`l.nop`
304			`l.nop`
305			`l.nop`
306			`l.nop`
307			`l.sys 0x7`
308			`l.nop`
309			`l.nop`
310			`l.sys 0x8`
311			`l.nop`
312			`l.nop`
313			`l.sys 0x9`
314			`l.nop`
315			`l.nop`
316			`l.sys 0xa`
317			`l.nop`
318			`l.nop`
319			`l.nop`
320			`l.sys 0xb`
321			`l.nop`
322			`l.nop`
323			`l.nop`
324			`l.nop`
325			`l.sys 0xc`
326			`l.nop`
327			`l.nop`
328			`l.sys 0xd`
329			`l.nop`
330			`l.nop`
331			`l.sys 0xe`
332			`l.nop`
333			`l.nop`
334			`l.sys 0xf`
335			`l.nop`
336			`/* Now turn off tick timer */`
337			`l.mtspr r0,r0,SPR_TTMR # clear TTMR`
338			`l.sfnei r16, 0x78 /* Should equal 120, 0x78 */`
339			`l.bf _fail`
340			`l.nop`
341			`l.movhi r3, hi(0x8000000d)`
342			`l.ori r3, r3, lo(0x8000000d)`
343	425	julius	`l.nop 2`
344			`l.ori r3, r0, 0`
345	349	julius	`l.nop 1`
346
347			`_fail:`
348			`l.movhi r3, hi(0xbaaaaaad)`
349			`l.ori r3, r3, lo(0xbaaaaaad)`
350			`l.nop 1`
351
352			`.global _syscall_function`
353			`_syscall_function:`
354			`/* r7 and r8 hold actual real ESR and EPCR, respectively */`
355			`/* We'll restore them now */`
356			`l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */`
357			`l.mtspr r0, r8, SPR_EPCR_BASE`
358			`l.add r16, r16, r3 /* Add syscall number to our counter */`
359	671	julius	`l.movhi r4, hi(0x00400000) /* 4MB mark of memory */`
360	349	julius	`/* Ensure memory access OK */`
361			`l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */`
362	671	julius	`l.add r4, r4, r3 /* Access this offset from 4MB mark */`
363	349	julius	`l.sw 0(r4), r16 /* Do a write to memory */`
364			`l.lwz r16, 0(r4) /* Do a read from memory */`
365			`/* Report running value of syscall counter */`
366			`l.or r3, r0, r16`
367			`l.nop 2`
368			`l.rfe /* Now continue from where we had the l.sys */`
369