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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ticksyscall.S] - Blame information for rev 545

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1 349 julius
#include "spr-defs.h"
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#include "board.h"
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4
/*
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6
        Tick timer and system call simultaneous interrupt test
7
 
8
        Within the test we'll use following global variables:
9
 
10
        r15 syscall interrupt counter
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        r16 syscall function counter
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        r17 timer interrupt counter
13
 
14
 
15
        The test do the following:
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        Setup tick interrupts to occur regularly, and then do a bunch of l.sys
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        systems calls, checking that they all occur OK
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19 477 julius
        Note: if this test appears to continue without counting, it's most
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        likely due to a tick counter value that's too small (processor is
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        executing too slowly, due to lack of cache or similar) and always
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        interrupting before execution can continue. Try increasing the
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        TICK_COUNTER_VALUE #define to give the processor time to continue.
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25 349 julius
        Julius Baxter, julius@opencores.org
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*/
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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55 477 julius
#define TICK_COUNTER_VALUE 16
56 349 julius
 
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58 477 julius
 
59 349 julius
/* =================================================== [ exceptions ] === */
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        .section .vectors, "ax"
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62
 
63
/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        /* Clear status register */
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        l.ori   r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Init the stack */
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        .global _stack
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        l.movhi r1, hi(_stack)
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        l.ori   r1, r1, lo(_stack)
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        l.addi  r2, r0, -3
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        l.and   r1, r1, r2
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        /* Jump to program initialisation code */
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        .global _start
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        l.movhi r4, hi(_start)
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        l.ori   r4, r4, lo(_start)
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        l.jr    r4
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        l.nop
83
 
84
 
85
/* =================================================== [ tick interrupt ] === */
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        .org 0x500
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        .global _tick_handler
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_tick_handler:
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        l.addi r17, r17, 1
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# Set r7 to hold value of TTMR, one-shot mode/single run (SR)
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        l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
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        l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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        l.add  r7,r5,r6
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        /* Report values , 0x00000500 == tick timer report*/
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        l.ori r3, r0, 0x0500
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        l.nop 2
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        l.or r3, r0, r17
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        l.nop 2
99
# Init the tick timer
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        l.mtspr r0,r0,SPR_TTCR          # clear TTCR
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        l.mtspr r0,r7,SPR_TTMR          # set TTMR
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        l.rfe
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104
/* ========================================================= [ syscall ] === */
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        .org 0xC00
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        .extern _syscall_function
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        .global _syscall_handler
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_syscall_handler:
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        l.addi r15, r15, 1
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        l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */
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        l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/
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        /* Unset IEE and TEE bits of SR */
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        l.ori r4, r0, SPR_SR_IEE|SPR_SR_TEE
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        l.ori r5, r0, 0xffff
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        l.xor r5, r5, r4
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        l.and r5, r7, r5 /* New SR without interrupt bits set */
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        l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */
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        /* Report values , 0x00000c00 == tick timer report*/
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        l.ori r3, r0, 0x0c00
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        l.nop 2
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        /* Get syscall number */
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        l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */
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        l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */
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        l.nop 2
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        l.movhi r4, hi(_syscall_function)
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        l.ori r4, r4, lo(_syscall_function)
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        l.mtspr r0, r4, SPR_EPCR_BASE
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        l.rfe
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130
 
131
 
132
/* =================================================== [ text section ] === */
133
        .section  .text
134
 
135
/* =================================================== [ start ] === */
136
 
137
        .global _start
138
_start:
139
 
140
        /* Instruction cache enable */
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        /* Check if IC present and skip enabling otherwise */
142
        l.mfspr r24,r0,SPR_UPR
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        l.andi  r26,r24,SPR_UPR_ICP
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        l.sfeq  r26,r0
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        l.bf    .L8
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        l.nop
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148
        /* Disable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_ICE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        /* Establish cache block size
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        If BS=0, 16;
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        If BS=1, 32;
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        r14 contain block size
159
        */
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        l.mfspr r24,r0,SPR_ICCFGR
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        l.andi  r26,r24,SPR_ICCFGR_CBS
162
        l.srli  r28,r26,7
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        l.ori   r30,r0,16
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        l.sll   r14,r30,r28
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166
        /* Establish number of cache sets
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        r16 contains number of cache sets
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        r28 contains log(# of cache sets)
169
        */
170
        l.andi  r26,r24,SPR_ICCFGR_NCS
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        l.srli  r28,r26,3
172
        l.ori   r30,r0,1
173
        l.sll   r16,r30,r28
174
 
175
        /* Invalidate IC */
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        l.addi  r6,r0,0
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        l.sll   r5,r14,r28
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.L7:
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        l.mtspr r0,r6,SPR_ICBIR
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        l.sfne  r6,r5
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        l.bf    .L7
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        l.add   r6,r6,r14
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185
        /* Enable IC */
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        l.mfspr r6,r0,SPR_SR
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        l.ori   r6,r6,SPR_SR_ICE
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        l.mtspr r0,r6,SPR_SR
189
        l.nop
190
        l.nop
191
        l.nop
192
        l.nop
193
        l.nop
194
        l.nop
195
        l.nop
196
        l.nop
197
 
198
.L8:
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        /* Data cache enable */
200
        /* Check if DC present and skip enabling otherwise */
201
        l.mfspr r24,r0,SPR_UPR
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        l.andi  r26,r24,SPR_UPR_DCP
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        l.sfeq  r26,r0
204
        l.bf    .L10
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        l.nop
206
        /* Disable DC */
207
        l.mfspr r6,r0,SPR_SR
208
        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r6,r5
211
        l.mtspr r0,r5,SPR_SR
212
        /* Establish cache block size
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           If BS=0, 16;
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           If BS=1, 32;
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           r14 contain block size
216
        */
217
        l.mfspr r24,r0,SPR_DCCFGR
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        l.andi  r26,r24,SPR_DCCFGR_CBS
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        l.srli  r28,r26,7
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        l.ori   r30,r0,16
221
        l.sll   r14,r30,r28
222
        /* Establish number of cache sets
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           r16 contains number of cache sets
224
           r28 contains log(# of cache sets)
225
        */
226
        l.andi  r26,r24,SPR_DCCFGR_NCS
227
        l.srli  r28,r26,3
228
        l.ori   r30,r0,1
229
        l.sll   r16,r30,r28
230
        /* Invalidate DC */
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        l.addi  r6,r0,0
232
        l.sll   r5,r14,r28
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.L9:
234
        l.mtspr r0,r6,SPR_DCBIR
235
        l.sfne  r6,r5
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        l.bf    .L9
237
        l.add   r6,r6,r14
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        /* Enable DC */
239
        l.mfspr r6,r0,SPR_SR
240
        l.ori   r6,r6,SPR_SR_DCE
241
        l.mtspr r0,r6,SPR_SR
242
.L10:
243
 
244
        // Kick off test
245
        l.jal   _main
246
        l.nop
247
 
248
/* =================================================== [ main ] === */
249
.global _main
250
_main:
251
        l.movhi r15, 0
252
        l.movhi r16, 0
253
        l.movhi r17, 0
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255
        #
256
        # unmask all ints
257
        #
258
        l.movhi r5,0xffff
259
        l.ori   r5,r5,0xffff
260
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
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262
        # Set r20 to hold enable exceptions and interrupts
263
        l.mfspr r20,r0,SPR_SR
264
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE
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266
        # Enable exceptions and interrupts
267
        l.mtspr r0,r20,SPR_SR   # set SR
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269
        # Set r7 to hold value of TTMR, one-shot mode/single run (SR)
270
        l.addi r5, r0, TICK_COUNTER_VALUE /* Tick timer counter value */
271
        l.movhi r6,hi(SPR_TTMR_SR | SPR_TTMR_IE)
272
        l.add  r7,r5,r6
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274
        # Init the tick timer
275
        l.mtspr r0,r0,SPR_TTCR          # clear TTCR
276
        l.mtspr r0,r7,SPR_TTMR          # set TTMR
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278
_wait_loop:
279
        l.sfeqi r17, 0x10
280
        l.bnf _wait_loop
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        l.nop
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283
        /* Timer is working, let's start with some syscalls */
284
        /* These should occur before tick timer's cycle is up */
285
        l.nop
286
        l.sys 0x1
287
        l.nop
288
        l.sys 0x2
289
        l.nop
290
        l.sys 0x3
291
        l.nop
292
        l.sys 0x4
293
        l.nop
294
        l.sys 0x5
295
        l.nop
296
        l.sfnei r16, 0xf /* Should equal 15, 0xf */
297
        l.bf _fail
298
        l.nop
299
        /* Continue, hopefuly now intercept tick timer cycles */
300
        l.nop
301
        l.nop
302
        l.sys 0x6
303
        l.nop
304
        l.nop
305
        l.nop
306
        l.nop
307
        l.sys 0x7
308
        l.nop
309
        l.nop
310
        l.sys 0x8
311
        l.nop
312
        l.nop
313
        l.sys 0x9
314
        l.nop
315
        l.nop
316
        l.sys 0xa
317
        l.nop
318
        l.nop
319
        l.nop
320
        l.sys 0xb
321
        l.nop
322
        l.nop
323
        l.nop
324
        l.nop
325
        l.sys 0xc
326
        l.nop
327
        l.nop
328
        l.sys 0xd
329
        l.nop
330
        l.nop
331
        l.sys 0xe
332
        l.nop
333
        l.nop
334
        l.sys 0xf
335
        l.nop
336
        /* Now turn off tick timer */
337
        l.mtspr r0,r0,SPR_TTMR          # clear TTMR
338
        l.sfnei r16, 0x78 /* Should equal 120, 0x78 */
339
        l.bf _fail
340
        l.nop
341
        l.movhi r3, hi(0x8000000d)
342
        l.ori r3, r3, lo(0x8000000d)
343 425 julius
        l.nop 2
344
        l.ori r3, r0, 0
345 349 julius
        l.nop 1
346
 
347
_fail:
348
        l.movhi r3, hi(0xbaaaaaad)
349
        l.ori r3, r3, lo(0xbaaaaaad)
350
        l.nop 1
351
 
352
        .global _syscall_function
353
_syscall_function:
354
        /* r7 and r8 hold actual real ESR and EPCR, respectively */
355
        /* We'll restore them now */
356
        l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */
357
        l.mtspr r0, r8, SPR_EPCR_BASE
358
        l.add r16, r16, r3 /* Add syscall number to our counter */
359
        l.movhi r4, hi(0x01000000) /* 16MB mark of memory */
360
        /* Ensure memory access OK */
361
        l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */
362
        l.add r4, r4, r3 /* Access this offset from 16MB mark */
363
        l.sw 0(r4), r16 /* Do a write to memory */
364
        l.lwz r16, 0(r4) /* Do a read from memory */
365
        /* Report running value of syscall counter */
366
        l.or r3, r0, r16
367
        l.nop 2
368
        l.rfe /* Now continue from where we had the l.sys */
369
 

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