OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [sdram/] [sim/] [sdram-banks.c] - Blame information for rev 393

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius
/*
2
 * SDRAM bank test
3
 *
4
 * Tests the extremeties of the SDRAM banks
5
 *
6
*/
7
 
8 393 julius
#include "cpu-utils.h"
9 349 julius
#include "board.h"
10
#include "sdram.h"
11
 
12
#define SDRAM_BANK_SIZE (SDRAM_SIZE / SDRAM_NUM_BANKS)
13
#define SDRAM_BANK_START(bank) ((SDRAM_BANK_SIZE*bank) + SDRAM_BASE)
14
#define SDRAM_BANK_LAST_WORD(bank) ((SDRAM_BANK_START((bank+1)))-4)
15
 
16
int main()
17
{
18
  report (SDRAM_SIZE);
19
  report (SDRAM_BANK_SIZE);
20
  report (SDRAM_BANK_START(0));
21
  report (SDRAM_BANK_LAST_WORD(0));
22
  report (SDRAM_BANK_START(1));
23
  report (SDRAM_BANK_LAST_WORD(1));
24
  report (SDRAM_BANK_START(2));
25
  report (SDRAM_BANK_LAST_WORD(2));
26
  report (SDRAM_BANK_START(3));
27
  report (SDRAM_BANK_LAST_WORD(3));
28
 
29
  REG32(SDRAM_BANK_LAST_WORD(0)) = 0x11111111;
30
  REG32(SDRAM_BANK_LAST_WORD(1)) = 0x22222222;
31
  REG32(SDRAM_BANK_LAST_WORD(2)) = 0x33333333;
32
  REG32(SDRAM_BANK_LAST_WORD(3)) = 0x44444444;
33
 
34
 
35
  unsigned long read_result = 0;
36
  read_result += REG32(SDRAM_BANK_LAST_WORD(0));
37
  read_result += REG32(SDRAM_BANK_LAST_WORD(1));
38
  read_result += REG32(SDRAM_BANK_LAST_WORD(2));
39
  read_result += REG32(SDRAM_BANK_LAST_WORD(3));
40
 
41
  exit((read_result-0x2aaaaa9d)); /* should result in 8000000d */
42
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.