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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [sdram/] [sim/] [sdram-cols.c] - Blame information for rev 393

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Line No. Rev Author Line
1 349 julius
/*
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 * SDRAM column test
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 *
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 * Tests accessing beginning and middle of column. Should detect any mismatch
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 * between SDRAM row size configuration.
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 *
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*/
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#include "or32-utils.h"
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#include "board.h"
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#include "sdram.h"
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// Start some rows after the program/data
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#define STACK_AT (128*1024)
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#define START_ROW  ((STACK_AT/SDRAM_ROW_SIZE)+1)
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// For a short test, set the following to 1
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#define SHORT_TEST 0
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#if SHORT_TEST==1
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# define SDRAM_NUM_ROWS (START_ROW + 512)
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#else
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# define SDRAM_NUM_ROWS (SDRAM_NUM_ROWS_PER_BANK * SDRAM_NUM_BANKS)
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#endif
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#define SDRAM_ROW_BEGINNING 0
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#define SDRAM_ROW_MIDDLE (SDRAM_ROW_SIZE/2)
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int main()
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{
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  int i; // Skip first 64KB, code/stack resides there
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  for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
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    {
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      REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_BEGINNING) = i;
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      REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_MIDDLE) = ~i;
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    }
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  int read_result = 0;
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  int read_result_inv = 0;
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  for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
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    {
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      read_result = REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_BEGINNING);
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      read_result_inv = REG32((i*(SDRAM_ROW_SIZE))+SDRAM_ROW_MIDDLE);
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      if ((read_result != i) || (read_result_inv != ~i))
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        {
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          report(0xbaaaaaad);
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          report(i);
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          report(read_result);
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          exit(0xbaaaaaad);
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        }
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    }
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  exit(0x8000000d);
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}

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