OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [sdram/] [sim/] [sdram-rows.c] - Blame information for rev 542

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius
/*
2
 * SDRAM row test
3
 *
4
 * Tests accessing every row
5
 *
6
*/
7
 
8 403 julius
#include "cpu-utils.h"
9 349 julius
#include "board.h"
10
#include "sdram.h"
11
 
12
#define SDRAM_NUM_ROWS (SDRAM_NUM_ROWS_PER_BANK * SDRAM_NUM_BANKS)
13
 
14
#define STACK_AT (128*1024)
15
#define START_ROW  ((STACK_AT/SDRAM_ROW_SIZE)+1)
16
 
17
int main()
18
{
19
 
20
  int i; // Skip first 64KB, code/stack resides there
21
  for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
22
    REG32((i*(SDRAM_ROW_SIZE))) = i;
23
 
24
  int read_result = 0;
25
 
26
  for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
27
    {
28
      read_result = REG32((i*(SDRAM_ROW_SIZE)));
29
      if (read_result != i)
30
        {
31
          report(0xbaaaaaad);
32
          report(i);
33
          report(read_result);
34
          exit(0xbaaaaaad);
35
        }
36
    }
37
  exit(0x8000000d);
38
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.