OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [sdram/] [sim/] [sdram.h] - Blame information for rev 669

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 393 julius
#ifndef _SDRAM_H_
2
#define _SDRAM_H_
3
 
4
#ifdef  MT48LC32M16A2 // 64MB SDRAM part
5
#define SDRAM_SIZE 0x04000000
6
#define SDRAM_ROW_SIZE 2048 // in bytes (10 bits col addr, 2 bytes per)
7
#define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address
8
#define SDRAM_NUM_BANKS 4
9
#endif
10
 
11
#ifdef  MT48LC16M16A2 // 32MB SDRAM part
12
#define SDRAM_SIZE 0x02000000
13
#define SDRAM_ROW_SIZE 1024 // in bytes (9 bits col addr, 2 bytes per)
14
#define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address
15
#define SDRAM_NUM_BANKS 4
16
#endif
17
 
18
#ifdef MT48LC4M16A2 // 8MB SDRAM part
19
#define SDRAM_SIZE 0x800000
20
#define SDRAM_ROW_SIZE 512 // in bytes (8 bits col addr, 2 bytes per)
21
#define SDRAM_NUM_ROWS_PER_BANK (4096) // 12-bit row address
22
#define SDRAM_NUM_BANKS 4
23
#endif
24
 
25
 
26
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.