OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [spi/] [board/] [simplespi-readflash.c] - Blame information for rev 542

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 415 julius
// Little program to dump the contents of the SPI flash memory it's connected 
2
// to on the board
3
 
4
#include "cpu-utils.h"
5
 
6
#include "board.h"
7
#include "uart.h"
8
#include "simple-spi.h"
9
#include "printf.h"
10
 
11
 
12
int spi_master;
13
char slave;
14
 
15
 
16
void
17
spi_write_ignore_read(int core, char dat)
18
{
19
  spi_core_write_data(core,dat);
20
  while (!(spi_core_data_avail(core))); // Wait for the transaction (should 
21
                                        // generate a byte)
22
  spi_core_read_data(core);
23
}
24
 
25
char
26
spi_read_ignore_write(int core)
27
{
28
  spi_core_write_data(core, 0x00);
29
  while (!(spi_core_data_avail(core))); // Wait for the transaction (should 
30
                                        // generate a byte)
31
  return spi_core_read_data(core);
32
}
33
 
34
 
35
unsigned long
36
spi_read_id(int core, char slave_sel)
37
{
38
  unsigned long rdid;
39
  char* rdid_ptr = (char*) &rdid;
40
  int i;
41
  spi_core_slave_select(core, slave_sel); // Select slave
42
  rdid_ptr[3] = 0;
43
  // Send the RDID command
44
  spi_write_ignore_read(core,0x9f); // 0x9f is READ ID command
45
  // Now we read the next 3 bytes
46
  for(i=0;i<3;i++)
47
    {
48
      rdid_ptr[i] = spi_read_ignore_write(core);
49
    }
50
  spi_core_slave_select(core, 0); // Deselect slave
51
  return rdid;
52
}
53
 
54
// Read status regsiter
55
char
56
spi_read_sr(int core, char slave_sel)
57
{
58
  char rdsr;
59
  spi_core_slave_select(core, slave_sel); // Select slave
60
  // Send the RDSR command
61
  spi_write_ignore_read(core,0x05); // 0x05 is READ status register command
62
  rdsr = spi_read_ignore_write(core);
63
  spi_core_slave_select(core, 0); // Deselect slave  
64
  return rdsr;
65
}
66
 
67
 
68
void
69
spi_read_block(int core, char slave_sel, unsigned int addr, int num_bytes,
70
               char* buf)
71
{
72
  int i;
73
  spi_core_slave_select(core, slave_sel); // Select slave
74
  spi_write_ignore_read(core, 0x3); // READ command
75
  spi_write_ignore_read(core,((addr >> 16) & 0xff)); // addres high byte
76
  spi_write_ignore_read(core,((addr >> 8) & 0xff)); // addres middle byte
77
  spi_write_ignore_read(core,((addr >> 0) & 0xff)); // addres low byte
78
  for(i=0;i<num_bytes;i++)
79
    buf[i] = spi_read_ignore_write(core);
80
 
81
  spi_core_slave_select(core, 0); // Deselect slave  
82
}
83
 
84
 
85
#define printhelp() printf("\nUsage: \n\t[d]ump\t\tdump 256 bytes of data to screen from flash\n\t[+/-]\t\tIncrease/decrease dump address by 256 bytes\n\t[</>]\t\tIncrease/decrease dump address by 4096 bytes\n\t[s]tatus\t\tprint status of SPI flash\n\n")
86
 
87
void
88
print_spi_status(void)
89
{
90
 
91
  printf("SPI core: %d\n",spi_master);
92
  printf("SPI slave select: 0x%x\n",slave&0xff);
93
 
94
  printf("SPI slave info:\n");
95
  printf("\tID:\t%x\n", spi_read_id(spi_master, slave));
96
  printf("\tSR:\t%x\n", spi_read_sr(spi_master, slave));
97
  printf("\n");
98
 
99
}
100
 
101
 
102
 
103
int
104
main()
105
{
106
 
107
  uart_init(0); // init the UART before we can printf
108
 
109
  volatile char c;
110
  int i,j;
111
  spi_master = 0;
112
  slave = 1;
113
 
114
  spi_core_slave_select(spi_master, 0); // Deselect slaves
115
 
116
  // Clear the read FIFO
117
  while (spi_core_data_avail(spi_master))
118
    c = spi_core_read_data(spi_master);
119
 
120
  // SPI core 0, should already be configured to read out data
121
  // when we reset.
122
 
123
  printf("\n\n\tSPI dumping app\n\n");
124
 
125
  unsigned long dump_addr = 0;
126
  char read_buf[256];
127
  int dump_amount = 0x100;
128
 
129
  while(1){
130
    printf("[d,+,-,s,h] > ");
131
    c = uart_getc(DEFAULT_UART);
132
 
133
    if ((c != '+') && (c != '-') && (c != '<') && (c != '>') )
134
      {
135
        printf("%c ",c);
136
        printf("\n");
137
      }
138
 
139
    if (c == 'h')
140
      printhelp();
141
    else if (c == 's')
142
      print_spi_status();
143
    else if (c == '+')
144
      {
145
        dump_addr += dump_amount;
146
        printf("dump_addr= 0x%x\r", dump_addr);
147
      }
148
    else if (c == '-')
149
      {
150
        dump_addr -= dump_amount;
151
        printf("dump_addr= 0x%x\r", dump_addr);
152
      }
153
    else if (c == '>')
154
      {
155
        dump_addr += dump_amount*16;
156
        printf("dump_addr= 0x%x\r", dump_addr);
157
      }
158
    else if (c == '<')
159
      {
160
        dump_addr -= dump_amount*16;
161
        printf("dump_addr= 0x%x\r", dump_addr);
162
      }
163
    else if (c == 'd')
164
      {
165
        spi_read_block(spi_master, 1, dump_addr, dump_amount, read_buf);
166
        // Print it out, 32 bytes across each time
167
        for(i=0;i<(dump_amount/32);i++)
168
          {
169
            printf("%.5x: ", (i*32)+dump_addr);
170
            for(j=0;j<32;j++)
171
              printf("%.2x", read_buf[(i*32)+j] & 0xff);
172
            printf("\n");
173
          }
174
        dump_addr += dump_amount;
175
 
176
 
177
      }
178
 
179
 
180
  }
181
 
182
  return 0;
183
 
184
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.