OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [spi/] [sim/] [spi-interrupt.c] - Blame information for rev 525

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius
#include "board.h"
2
#include "spr-defs.h"
3 403 julius
#include "cpu-utils.h"
4 349 julius
#include "simple-spi.h"
5
#include "int.h"
6
 
7
#include "simple-spi.h"
8
 
9
 
10 403 julius
#include "orpsoc-defines.h"
11 349 julius
 
12
// Detect which of the SPI cores are enabled, tailor the test for that
13
#ifndef SPI1
14
# ifndef SPI2
15
#  error
16
#  error No SPI cores to test with! Please enable SPI1 and/or SPI2
17
#  error
18
# else
19
#  define NUM_SPI_CORES 1
20
#  define FIRST_SPI_CORE 2
21
# endif
22
#else
23
# ifdef SPI2
24
#  define NUM_SPI_CORES 2
25
#  define FIRST_SPI_CORE 1
26
# else
27
#  define NUM_SPI_CORES 1
28
#  define FIRST_SPI_CORE 1
29
# endif
30
#endif
31
 
32
 
33
struct spi_int_data{
34
  unsigned long data;
35
  char retrieved;
36
};
37
 
38
volatile struct spi_int_data spi1_int_data;
39
 
40
void spi1_int_handler(void);
41
 
42
void spi1_int_handler(void)
43
{
44
 
45
  // Should have recieved 4 bytes, let's pull them off and put them into
46
  // the data struct
47
  char* spi1_data = (char*) &spi1_int_data.data;
48
  int i;
49
  for (i=0;i<4;i++)
50
    {
51
      while (!spi_core_data_avail(1));
52
      spi1_data[i] = spi_core_read_data(1);
53
    }
54
 
55
  spi1_int_data.retrieved = 1;
56
 
57
  // Clear the interrupt flag
58
  spi_core_interrupt_flag_clear(1);
59
 
60
  return;
61
}
62
 
63
volatile struct spi_int_data spi2_int_data;
64
 
65
void spi2_int_handler(void);
66
 
67
void spi2_int_handler(void)
68
{
69
 
70
  // Should have recieved 4 bytes, let's pull them off and put them into
71
  // the data struct
72
  char* spi2_data = (char*) &spi2_int_data.data;
73
  int i;
74
  for (i=0;i<4;i++)
75
    {
76
      while (!spi_core_data_avail(2));
77
      spi2_data[i] = spi_core_read_data(2);
78
    }
79
 
80
  spi2_int_data.retrieved = 1;
81
 
82
  // Clear the interrupt flag
83
  spi_core_interrupt_flag_clear(2);
84
 
85
  return;
86
}
87
 
88
 
89
int main()
90
{
91
  int spi_master;
92
  int spi_slave = 2;
93
  int i,j;
94
 
95
  spi1_int_data.retrieved = 0;
96
  spi2_int_data.retrieved = 0;
97
 
98
  int_init();
99
 
100
  /* Install SPI core 1 interrupt handler */
101
  int_add(SPI1_IRQ, spi1_int_handler, 0);
102
 
103
  /* Install SPI core 2 interrupt handler */
104
  int_add(SPI2_IRQ, spi2_int_handler, 0);
105
 
106
  /* Enable interrupts in supervisor register */
107
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
108
 
109
 
110
  for (spi_master = FIRST_SPI_CORE;
111
       spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
112
       spi_master++)
113
    {
114
 
115
      // Init master -- disable it first
116
      spi_core_disable(spi_master);
117
      // polarity, phase, dividers :
118
      spi_core_clock_setup(spi_master, 0, 0, 0, 0);
119
      // Set number of transfers per interrupt to 4
120
      spi_core_set_int_count(spi_master, SIMPLESPI_SPER_ICNT_FOUR);
121
 
122
      // Enable interrupts on the core
123
      spi_core_interrupt_enable(spi_master);
124
 
125
      // Now enable core after configuration, before using it
126
      spi_core_enable(spi_master);
127
    }
128
 
129
  // Play with the slaves
130
  for(i=0;i<16;i++)
131
    {
132
      for (spi_master = FIRST_SPI_CORE;
133
           spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
134
           spi_master++)
135
        {
136
 
137
          spi_slave = i % 3;
138
          spi_slave = (1 << spi_slave);
139
          for(j=0;j<4;j++)
140
            {
141
              // Select a slave on SPI bus
142
              spi_core_slave_select(spi_master, spi_slave);
143
              // Do a SPI bus transaction - we're only reading
144
              // coming back
145
              while (!spi_core_write_avail(spi_master));
146
              spi_core_write_data(spi_master, (i&0xff));
147
              // Deselect all masters
148
              spi_core_slave_select(spi_master, 0);
149
            }
150
          // Wait for the interrupt to retrieve the data and signal this
151
 
152
          if (spi_master == 1){
153
            while (!spi1_int_data.retrieved);
154
            // Now report it
155
            report(spi1_int_data.data);
156
            // And reset the retrieved bit
157
            spi1_int_data.retrieved = 0;
158
          }
159
          if (spi_master == 2){
160
            while (!spi2_int_data.retrieved);
161
            // Now report it
162
            report(spi2_int_data.data);
163
            // And reset the retrieved bit
164
            spi2_int_data.retrieved = 0;
165
          }
166
        }
167
    }
168
 
169
  exit(0x8000000d);
170
 
171
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.