OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [uart/] [sim/] [uart-interruptloopback.c] - Blame information for rev 714

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 439 julius
/*
2
 * UART loopback interrupt test
3
 *
4
 * Tests UART and interrupt routines servicing them.
5
 *
6
 * Relies on testbench having uart0's lines in loopback (rx = tx)
7
 *
8
 * Julius Baxter, julius.baxter@orsoc.se
9
 *
10
*/
11
 
12
 
13
#include "cpu-utils.h"
14
#include "spr-defs.h"
15
#include "board.h"
16
#include "uart.h"
17
#include "int.h"
18
#include "orpsoc-defines.h"
19
 
20
#ifndef UART0
21
# error
22
# error UART0 missing and is required for UART interrupt (loopback) test
23
# error
24
#endif
25
 
26
struct uart_tx_ctrl
27
{
28
  char *bufptr;
29
  int busy;
30
};
31
 
32
volatile struct uart_tx_ctrl uart0_tx_ctrl;
33
 
34
void uart_int_handler(void* corenum);
35
 
36
void uart_int_handler(void* corenum)
37
{
38
 
39
  int core = *((int*)corenum);
40
 
41
  if (core)report(core);
42
 
43
  char iir = uart_get_iir(core);
44
 
45
  if ( (iir & UART_IIR_RLSI)  == UART_IIR_RLSI)
46
    uart_get_lsr(core); // Should clear this interrupt
47
  else if ( (iir & UART_IIR_RDI) == UART_IIR_RDI )
48
    {
49
      // Was potentially also a timeout. Do we care?
50
 
51
      // Data received. Pull all from the FIFO buffer, here we just report it
52
      // and throw it away
53
      char rxchar;
54
      while (uart_check_for_char(core))
55
        {
56
          rxchar = uart_getc(core);
57
          report(0xff & rxchar);
58
          if (rxchar == 0x2a) // Exit simulation when RX char is '*'
59
            {
60
              report(0x8000000d);
61
              exit(0);
62
            }
63
        }
64
    }
65
  else if ( (iir & UART_IIR_THRI) ==  UART_IIR_THRI)
66
    {
67
      // Only trigered if we've set something to be transmitted
68
      // and enabled the interrupt.
69
      // Put next thing to be transmitted into buffer, check if it's
70
      // the last, if so, disable interrupts.
71
      if (uart0_tx_ctrl.bufptr[0] == 0) // EOL, disable interrupt after this char
72
        {
73
          uart_txint_disable(core);
74
          uart0_tx_ctrl.busy = 0;
75
        }
76
      else // Transmit this byte
77
        {
78
          uart_putc_noblock(core, uart0_tx_ctrl.bufptr[0]);
79
          uart0_tx_ctrl.bufptr++;
80
        }
81
    }
82
  else if ( (iir & UART_IIR_MSI) == UART_IIR_MSI )
83
    {
84
      // Just read the modem status register to clear this
85
      uart_get_msr(core);
86
    }
87
}
88
 
89
 
90
void uart0_tx_buffer(char* buf)
91
{
92
  while (uart0_tx_ctrl.busy); // Wait until we can transmit more
93
  uart0_tx_ctrl.bufptr = buf;
94
  uart0_tx_ctrl.busy = 1;
95
  uart_txint_enable(0);
96
}
97
 
98
int main()
99
{
100
  int uart0_core = 0;
101
  int uart1_core = 1;
102
  uart0_tx_ctrl.busy = 0;
103
 
104
  /* Set up interrupt handler */
105
  int_init();
106
 
107
  /* Install UART core 0 interrupt handler */
108
  int_add(UART0_IRQ, uart_int_handler,(void*) &uart0_core);
109
 
110
  /* Install UART core 1 interrupt handler */
111
  //int_add(UART1_IRQ, uart_int_handler,(void*) &uart1_core);
112
 
113
  /* Enable interrupts in supervisor register */
114
  mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
115
 
116
  uart_init(uart0_core);
117
  //uart_init(uart1_core);
118
 
119
  //uart_rxint_enable(uart1_core);
120
  uart_rxint_enable(uart0_core);
121
 
122
  char* teststring = "\n\tHello world from UART 0\n\0";
123
 
124
  uart0_tx_buffer(teststring);
125
 
126
  // Do other things while we transmit
127
  float f1, f2, f3; int i;
128
  f1 = 0.2382; f2 = 4342.65; f3=0;
129
  for(i=0;i<32;i++) f3 += f1*f3 + f2;
130
 
131
  report(f3);
132
  report(0x4aaaaa1f);
133
 
134
  char* done_calculating = "\tDone with the number crunching!\n\0";
135
 
136
  uart0_tx_buffer(done_calculating);
137
 
138
  // Character '*', which will be received in the interrupt handler and cause
139
  // the simulation to exit.
140
  char* finish = "*\n\0";
141
 
142
  uart0_tx_buffer(finish);
143
 
144
  while(1); // will exit in the rx interrupt routine
145
 
146
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.