OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [calmrisc16.html] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 unneback
<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
2
<!-- This material may be distributed only subject to the terms      -->
3
<!-- and conditions set forth in the Open Publication License, v1.0  -->
4
<!-- or later (the latest version is presently available at          -->
5
<!-- http://www.opencontent.org/openpub/).                           -->
6
<!-- Distribution of the work or derivative of the work in any       -->
7
<!-- standard (paper) book form is prohibited unless prior           -->
8
<!-- permission is obtained from the copyright holder.               -->
9
<HTML
10
><HEAD
11
><TITLE
12
>CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board </TITLE
13
><meta name="MSSmartTagsPreventParsing" content="TRUE">
14
<META
15
NAME="GENERATOR"
16
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
17
"><LINK
18
REL="HOME"
19
TITLE="eCos Reference Manual"
20
HREF="ecos-ref.html"><LINK
21
REL="UP"
22
TITLE="Installation and Testing"
23
HREF="installation-and-testing.html"><LINK
24
REL="PREVIOUS"
25
TITLE="ARM/Xscale Intel IQ80321"
26
HREF="iq80321.html"><LINK
27
REL="NEXT"
28
TITLE="CalmRISC/CalmRISC32 Samsung CalmRISC32 Core Evaluation Board "
29
HREF="calmrisc32.html"></HEAD
30
><BODY
31
CLASS="SECT1"
32
BGCOLOR="#FFFFFF"
33
TEXT="#000000"
34
LINK="#0000FF"
35
VLINK="#840084"
36
ALINK="#0000FF"
37
><DIV
38
CLASS="NAVHEADER"
39
><TABLE
40
SUMMARY="Header navigation table"
41
WIDTH="100%"
42
BORDER="0"
43
CELLPADDING="0"
44
CELLSPACING="0"
45
><TR
46
><TH
47
COLSPAN="3"
48
ALIGN="center"
49
>eCos Reference Manual</TH
50
></TR
51
><TR
52
><TD
53
WIDTH="10%"
54
ALIGN="left"
55
VALIGN="bottom"
56
><A
57
HREF="iq80321.html"
58
ACCESSKEY="P"
59
>Prev</A
60
></TD
61
><TD
62
WIDTH="80%"
63
ALIGN="center"
64
VALIGN="bottom"
65
>Chapter 5. Installation and Testing</TD
66
><TD
67
WIDTH="10%"
68
ALIGN="right"
69
VALIGN="bottom"
70
><A
71
HREF="calmrisc32.html"
72
ACCESSKEY="N"
73
>Next</A
74
></TD
75
></TR
76
></TABLE
77
><HR
78
ALIGN="LEFT"
79
WIDTH="100%"></DIV
80
><DIV
81
CLASS="SECT1"
82
><H1
83
CLASS="SECT1"
84
><A
85
NAME="CALMRISC16">CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board</H1
86
><DIV
87
CLASS="SECT2"
88
><H2
89
CLASS="SECT2"
90
><A
91
NAME="AEN6447">Overview</H2
92
><P
93
> The
94
Samsung CalmRISC16 evaluation platform consists of two boards connected by a
95
ribbon cable. One board contains the CPU core and memory. The other board is
96
called the MDSChip board and provides the host interface. The calmRISC16 is a
97
harvard architecture with separate 22-bit program and data addresses. The
98
instruction set provides no instruction for writing to program memory. The
99
MDSChip board firmware (called CalmBreaker) provides a pseudo register interface
100
so that code running on the core has access to a serial channel and a mechanism
101
to write to program memory. The serial channel is fixed at 57600-8-N-1 by the
102
firmware. The CalmBreaker firmware also provides a serial protocol which
103
allows a host to download a program and to start or stop the core board.</P
104
><P
105
>The following RedBoot configurations are supported:
106
 
107
      <DIV
108
CLASS="INFORMALTABLE"
109
><A
110
NAME="AEN6457"><P
111
></P
112
><TABLE
113
BORDER="1"
114
CLASS="CALSTABLE"
115
><THEAD
116
><TR
117
><TH
118
ALIGN="LEFT"
119
VALIGN="TOP"
120
>Configuration</TH
121
><TH
122
ALIGN="LEFT"
123
VALIGN="TOP"
124
>Mode</TH
125
><TH
126
ALIGN="LEFT"
127
VALIGN="TOP"
128
>Description</TH
129
><TH
130
ALIGN="LEFT"
131
VALIGN="TOP"
132
>File</TH
133
></TR
134
></THEAD
135
><TBODY
136
><TR
137
><TD
138
ALIGN="LEFT"
139
VALIGN="TOP"
140
>ROM</TD
141
><TD
142
ALIGN="LEFT"
143
VALIGN="TOP"
144
>[ROM]</TD
145
><TD
146
ALIGN="LEFT"
147
VALIGN="TOP"
148
>RedBoot running via the MDSChip board.</TD
149
><TD
150
ALIGN="LEFT"
151
VALIGN="TOP"
152
>redboot_ROM.ecm</TD
153
></TR
154
></TBODY
155
></TABLE
156
><P
157
></P
158
></DIV
159
></P
160
></DIV
161
><DIV
162
CLASS="SECT2"
163
><H2
164
CLASS="SECT2"
165
><A
166
NAME="AEN6471">Initial Installation Method</H2
167
><P
168
>The CalmRISC16 core is controlled through the MDSChip board. There is
169
no non-volatile storage available for RedBoot, so RedBoot must be downloaded
170
to the board on every power cycle. A small utility program is used to download
171
S-record files to the eval board. Sources and build instructions for this
172
utility are located in the RedBoot sources in:
173
<TT
174
CLASS="FILENAME"
175
>packages/hal/calmrisc16/ceb/current/support</TT
176
></P
177
><P
178
>To download the RedBoot image, first press the reset button on the MDSChip
179
board. The green 'Run' LED on the core board should go off. Now, use the
180
utility to download the RedBoot image with:
181
<TABLE
182
BORDER="5"
183
BGCOLOR="#E0E0F0"
184
WIDTH="70%"
185
><TR
186
><TD
187
><PRE
188
CLASS="SCREEN"
189
>$ <TT
190
CLASS="USERINPUT"
191
><B
192
>calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf</B
193
></TT
194
></PRE
195
></TD
196
></TR
197
></TABLE
198
>
199
Note that the '-p /dev/term/b' specifies the serial port to use and will vary
200
from system to system. The download will take about two minutes. After it
201
finishes, start RedBoot with:
202
<TABLE
203
BORDER="5"
204
BGCOLOR="#E0E0F0"
205
WIDTH="70%"
206
><TR
207
><TD
208
><PRE
209
CLASS="SCREEN"
210
>$ <TT
211
CLASS="USERINPUT"
212
><B
213
>calmbreaker -p /dev/term/b --run</B
214
></TT
215
></PRE
216
></TD
217
></TR
218
></TABLE
219
>
220
The 'Run' LED on the core board should be on. Connecting to the MDSboard with
221
a terminal and typing enter should result in RedBoot reprinting the command
222
prompt.</P
223
></DIV
224
><DIV
225
CLASS="SECT2"
226
><H2
227
CLASS="SECT2"
228
><A
229
NAME="AEN6480">Special RedBoot Commands</H2
230
><P
231
>None.</P
232
></DIV
233
><DIV
234
CLASS="SECT2"
235
><H2
236
CLASS="SECT2"
237
><A
238
NAME="AEN6483">Special Note on Serial Channel</H2
239
><P
240
>The MDSChip board uses a relatively slow microcontroller to provide
241
the pseudo-register interface to the core board. This pseudo-register
242
interface provides access to the serial channel and write access to program
243
memory. Those interfaces are slow and the serial channel is easily overrun
244
by a fast host. For this reason, GDB must be told to limit the size of code
245
download packets to avoid serial overrun. This is done with the following
246
GDB command:
247
<TABLE
248
BORDER="5"
249
BGCOLOR="#E0E0F0"
250
WIDTH="70%"
251
><TR
252
><TD
253
><PRE
254
CLASS="SCREEN"
255
>(gdb) <TT
256
CLASS="USERINPUT"
257
><B
258
>set download-write-size 25</B
259
></TT
260
></PRE
261
></TD
262
></TR
263
></TABLE
264
></P
265
></DIV
266
><DIV
267
CLASS="SECT2"
268
><H2
269
CLASS="SECT2"
270
><A
271
NAME="AEN6488">Rebuilding RedBoot</H2
272
><P
273
>These shell variables provide the platform-specific information
274
needed for building RedBoot according to the procedure described in
275
<A
276
HREF="rebuilding-redboot.html"
277
>Chapter 3</A
278
>:
279
<TABLE
280
BORDER="5"
281
BGCOLOR="#E0E0F0"
282
WIDTH="70%"
283
><TR
284
><TD
285
><PRE
286
CLASS="PROGRAMLISTING"
287
>export TARGET=calm16_ceb
288
export ARCH_DIR=calmrisc16
289
export PLATFORM_DIR=ceb</PRE
290
></TD
291
></TR
292
></TABLE
293
></P
294
><P
295
>The names of configuration files are listed above with the
296
description of the associated modes.</P
297
></DIV
298
></DIV
299
><DIV
300
CLASS="NAVFOOTER"
301
><HR
302
ALIGN="LEFT"
303
WIDTH="100%"><TABLE
304
SUMMARY="Footer navigation table"
305
WIDTH="100%"
306
BORDER="0"
307
CELLPADDING="0"
308
CELLSPACING="0"
309
><TR
310
><TD
311
WIDTH="33%"
312
ALIGN="left"
313
VALIGN="top"
314
><A
315
HREF="iq80321.html"
316
ACCESSKEY="P"
317
>Prev</A
318
></TD
319
><TD
320
WIDTH="34%"
321
ALIGN="center"
322
VALIGN="top"
323
><A
324
HREF="ecos-ref.html"
325
ACCESSKEY="H"
326
>Home</A
327
></TD
328
><TD
329
WIDTH="33%"
330
ALIGN="right"
331
VALIGN="top"
332
><A
333
HREF="calmrisc32.html"
334
ACCESSKEY="N"
335
>Next</A
336
></TD
337
></TR
338
><TR
339
><TD
340
WIDTH="33%"
341
ALIGN="left"
342
VALIGN="top"
343
>ARM/Xscale Intel IQ80321</TD
344
><TD
345
WIDTH="34%"
346
ALIGN="center"
347
VALIGN="top"
348
><A
349
HREF="installation-and-testing.html"
350
ACCESSKEY="U"
351
>Up</A
352
></TD
353
><TD
354
WIDTH="33%"
355
ALIGN="right"
356
VALIGN="top"
357
>CalmRISC/CalmRISC32 Samsung CalmRISC32 Core Evaluation Board</TD
358
></TR
359
></TABLE
360
></DIV
361
></BODY
362
></HTML
363
>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.