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<HTML
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>Architecture, Variant and Platform</TITLE
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TITLE="The eCos Hardware Abstraction Layer (HAL)"
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>eCos Reference Manual</TH
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><H1
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><A
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NAME="HAL-ARCHITECTURE-VARIANT-AND-PLATFORM">Chapter 7. Architecture, Variant and Platform</H1
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><P
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>We have identified three levels at which the HAL must operate.</P
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><P
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></P
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><UL
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><LI
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><P
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>    The <I
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>architecture
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    HAL</I
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> abstracts the basic CPU architecture and includes
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    things like interrupt delivery, context switching, CPU startup
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    etc.
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    </P
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></LI
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><LI
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><P
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>    The  <I
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>variant HAL</I
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>
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    encapsulates features of the CPU variant such as caches, MMU and
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    FPU features. It also deals with any on-chip peripherals such as
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    memory and interrupt controllers. For architectural variations,
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    the actual implementation of the variation is often in the
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    architectural HAL, and the variant HAL simply provides the correct
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    configuration definitions.
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    </P
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></LI
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><LI
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><P
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>    The <I
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>platform HAL</I
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>
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    abstracts the properties of the current platform and includes
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    things like platform startup, timer devices, I/O register access
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    and interrupt controllers.
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    </P
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><P
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>The boundaries between these three HAL levels are necessarily blurred
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since functionality shifts between levels on a target-by-target basis.
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For example caches and MMU may be either an architecture feature or a
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variant feature. Similarly, memory and interrupt controllers may be
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on-chip and in the variant HAL, or off-chip and in the platform HAL.</P
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><P
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>Generally there is a separate package for each of the architecture,
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variant and package HALs for a target. For some of the older targets,
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or where it would be essentially empty, the variant HAL is omitted.</P
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