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<HTML
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><HEAD
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><TITLE
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>Future developments</TITLE
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"><LINK
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REL="HOME"
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TITLE="eCos Reference Manual"
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HREF="ecos-ref.html"><LINK
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REL="UP"
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TITLE="The eCos Hardware Abstraction Layer (HAL)"
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HREF="the-ecos-hardware-abstraction-layer.html"><LINK
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REL="PREVIOUS"
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TITLE="Architecture HAL Porting"
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HREF="hal-porting-architecture.html"><LINK
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TITLE="The ISO Standard C and Math Libraries"
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>eCos Reference Manual</TH
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>Prev</A
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><TD
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WIDTH="80%"
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VALIGN="bottom"
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WIDTH="10%"
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ALIGN="right"
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VALIGN="bottom"
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>Next</A
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><H1
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><A
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NAME="HAL-FUTURE-DEVELOPMENTS">Chapter 12. Future developments</H1
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><P
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>The HAL is not complete, and will evolve and increase over
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time. Among the intended developments are:</P
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><P
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></P
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><UL
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><LI
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><P
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>Common macros for interpreting the contents of a saved
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machine context. These would allow portable code, such as debug
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stubs, to extract such values as the program counter and stack pointer
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from a state without having to interpret a <SPAN
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CLASS="STRUCTNAME"
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>HAL_SavedRegisters</SPAN
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> structure
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directly.</P
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></LI
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><LI
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><P
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>Debugging support. Macros to set and clear hardware and
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software breakpoints. Access to other areas of machine state may
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also be supported.</P
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></LI
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><LI
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><P
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>Static initialization support. The current HAL provides a
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dynamic interface to things like thread context initialization and ISR
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attachment. We also need to be able to define the system entirely
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statically so that it is ready to go on restart, without needing to
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run code. This will require extra macros to define these
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initializations. Such support may have a consequential effect on the
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current HAL specification.</P
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></LI
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><LI
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><P
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>CPU state control. Many CPUs have both kernel and user
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states. Although it is not intended to run any code in user state
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for the foreseeable future, it is possible that this may happen
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eventually. If this is the case, then some minor changes may be needed
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to the current HAL API to accommodate this. These should mostly
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be extensions, but minor changes in semantics may also be required.</P
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></LI
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><LI
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><P
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>Physical memory management. Many embedded systems have
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multiple memory areas with varying properties such as base address,
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size, speed, bus width, cacheability and persistence. An API is
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needed to support the discovery of this information about the machine's
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physical memory map.</P
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></LI
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><LI
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><P
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>Memory management control. Some embedded processors have
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a memory management unit. In some cases this must be enabled to
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allow the cache to be controlled, particularly if different regions
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of memory must have different caching properties. For some purposes,
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in some systems, it will be useful to manipulate the MMU settings
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dynamically.</P
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></LI
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><LI
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><P
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>Power management. Macros to access and control any power
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management mechanisms available on the CPU implementation. These
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would provide a substrate for a more general power management system
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that also involved device drivers and other hardware components.</P
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></LI
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><LI
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><P
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>Generic serial line macros. Most serial line devices operate
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in the same way, the only real differences being exactly which bits
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in which registers perform the standard functions. It should be
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possible to develop a set of HAL macros that provide basic serial
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line services such as baud rate setting, enabling interrupts, polling
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for transmit or receive ready, transmitting and receiving data etc.
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Given these it should be possible to create a generic serial line
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device driver that will allow rapid bootstrapping on any new platform.
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It may be possible to extend this mechanism to other device types.</P
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></LI
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