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<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
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<HTML
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><HEAD
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><TITLE
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>HAL I/O</TITLE
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TITLE="eCos Reference Manual"
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REL="UP"
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TITLE="HAL Interfaces"
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HREF="hal-interfaces.html"><LINK
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TITLE="Interrupt Handling"
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><TR
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>eCos Reference Manual</TH
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><TR
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><TD
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ALIGN="left"
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><A
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HREF="hal-interrupt-handling.html"
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ACCESSKEY="P"
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>Prev</A
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></TD
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><TD
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WIDTH="80%"
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ALIGN="center"
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VALIGN="bottom"
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>Chapter 9. HAL Interfaces</TD
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><TD
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ALIGN="right"
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VALIGN="bottom"
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><A
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><DIV
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CLASS="SECTION"
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><H1
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CLASS="SECTION"
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><A
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NAME="HAL-INPUT-AND-OUTPUT">HAL I/O</H1
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><P
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>This section contains definitions for supporting access
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to device control registers in an architecture neutral
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fashion.</P
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><P
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>These definitions are normally found in the header file
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<TT
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CLASS="FILENAME"
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>cyg/hal/hal_io.h</TT
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>.  This file itself contains
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macros that are generic to the architecture. If there are variant or
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platform specific IO access macros then these will be found in
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<TT
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CLASS="FILENAME"
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>cyg/hal/var_io.h</TT
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> and
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<TT
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CLASS="FILENAME"
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>cyg/hal/plf_io.h</TT
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> in the variant or platform HALs
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respectively. These files are include automatically by this header, so
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need not be included explicitly.</P
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><P
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>This header (or more likely <TT
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CLASS="FILENAME"
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>cyg/hal/plf_io.h</TT
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>) also
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defines the PCI access macros. For more information on these see <A
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HREF="pci-library-reference.html"
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>the Section called <I
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>PCI Library reference</I
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> in Chapter 30</A
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>.</P
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN8057">Register address</H2
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><TABLE
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>HAL_IO_REGISTER</PRE
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></TD
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></TR
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></TABLE
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><P
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>This type is used to store the address of an I/O register. It will
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normally be a memory address, an integer port address or an offset
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into an I/O space. More complex architectures may need to code an
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address space plus offset pair into a single word, or may represent it
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as a structure.</P
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><P
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>Values of variables and constants of this type will usually be
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supplied by configuration mechanisms or in target specific headers.</P
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></DIV
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN8062">Register read</H2
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><TABLE
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>HAL_READ_XXX( register, value )
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HAL_READ_XXX_VECTOR( register, buffer, count, stride )</PRE
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></TD
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></TR
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></TABLE
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><P
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>These macros support the reading of I/O registers in various
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sizes. The <TT
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CLASS="REPLACEABLE"
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><I
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>XXX</I
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></TT
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> component of the name may be
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<TT
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CLASS="LITERAL"
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>UINT8</TT
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>, <TT
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CLASS="LITERAL"
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>UINT16</TT
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>,
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<TT
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CLASS="LITERAL"
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>UINT32</TT
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>.</P
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><P
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><TT
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CLASS="FUNCTION"
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>HAL_READ_XXX()</TT
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> reads the appropriately sized
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value from the register and stores it in the variable passed as the
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second argument.</P
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><P
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><TT
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CLASS="FUNCTION"
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>HAL_READ_XXX_VECTOR()</TT
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> reads
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<TT
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CLASS="PARAMETER"
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><I
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>count</I
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></TT
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> values of the appropriate size into
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<TT
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CLASS="PARAMETER"
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><I
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>buffer</I
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></TT
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>. The <TT
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CLASS="PARAMETER"
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><I
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>stride</I
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></TT
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>
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controls how the pointer advances through the register space. A stride
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of zero will read the same register repeatedly, and a stride of one
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will read adjacent registers of the given size. Greater strides will
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step by larger amounts, to allow for sparsely mapped registers for
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example.</P
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></DIV
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN8077">Register write</H2
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><TABLE
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WIDTH="70%"
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>HAL_WRITE_XXX( register, value )
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HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )</PRE
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></TD
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></TR
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></TABLE
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><P
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>These macros support the writing of I/O registers in various
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sizes. The <TT
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CLASS="REPLACEABLE"
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><I
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>XXX</I
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></TT
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> component of the name may be
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<TT
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CLASS="LITERAL"
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>UINT8</TT
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>, <TT
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CLASS="LITERAL"
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>UINT16</TT
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>,
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<TT
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CLASS="LITERAL"
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>UINT32</TT
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>.</P
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><P
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><TT
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CLASS="FUNCTION"
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>HAL_WRITE_XXX()</TT
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> writes
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the appropriately sized value from the variable passed as the second argument
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stored it in the register.</P
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><P
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><TT
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CLASS="FUNCTION"
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>HAL_WRITE_XXX_VECTOR()</TT
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> writes
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<TT
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CLASS="PARAMETER"
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><I
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>count</I
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></TT
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> values of the appropriate size from <TT
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CLASS="PARAMETER"
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><I
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>buffer</I
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></TT
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>. The <TT
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CLASS="PARAMETER"
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><I
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>stride</I
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></TT
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> controls
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how the pointer advances through the register space. A stride of
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zero will write the same register repeatedly, and a stride of one
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will write adjacent registers of the given size. Greater strides
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will step by larger amounts, to allow for sparsely mapped registers
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for example.</P
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></DIV
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>Prev</A
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>Interrupt Handling</TD
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>Up</A
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