OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [hal-input-and-output.html] - Blame information for rev 593

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 unneback 
<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
2 
<!-- This material may be distributed only subject to the terms      -->
3 
<!-- and conditions set forth in the Open Publication License, v1.0  -->
4 
<!-- or later (the latest version is presently available at          -->
5 
<!-- http://www.opencontent.org/openpub/).                           -->
6 
<!-- Distribution of the work or derivative of the work in any       -->
7 
<!-- standard (paper) book form is prohibited unless prior           -->
8 
<!-- permission is obtained from the copyright holder.               -->
9 
<HTML
10 
><HEAD
11 
><TITLE
12 
>HAL I/O</TITLE
13 
><meta name="MSSmartTagsPreventParsing" content="TRUE">
14 
<META
15 
NAME="GENERATOR"
16 
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
17 
"><LINK
18 
REL="HOME"
19 
TITLE="eCos Reference Manual"
20 
HREF="ecos-ref.html"><LINK
21 
REL="UP"
22 
TITLE="HAL Interfaces"
23 
HREF="hal-interfaces.html"><LINK
24 
REL="PREVIOUS"
25 
TITLE="Interrupt Handling"
26 
HREF="hal-interrupt-handling.html"><LINK
27 
REL="NEXT"
28 
TITLE="Cache Control"
29 
HREF="hal-cache-control.html"></HEAD
30 
><BODY
31 
CLASS="SECTION"
32 
BGCOLOR="#FFFFFF"
33 
TEXT="#000000"
34 
LINK="#0000FF"
35 
VLINK="#840084"
36 
ALINK="#0000FF"
37 
><DIV
38 
CLASS="NAVHEADER"
39 
><TABLE
40 
SUMMARY="Header navigation table"
41 
WIDTH="100%"
42 
BORDER="0"
43 
CELLPADDING="0"
44 
CELLSPACING="0"
45 
><TR
46 
><TH
47 
COLSPAN="3"
48 
ALIGN="center"
49 
>eCos Reference Manual</TH
50 
></TR
51 
><TR
52 
><TD
53 
WIDTH="10%"
54 
ALIGN="left"
55 
VALIGN="bottom"
56 
><A
57 
HREF="hal-interrupt-handling.html"
58 
ACCESSKEY="P"
59 
>Prev</A
60 
></TD
61 
><TD
62 
WIDTH="80%"
63 
ALIGN="center"
64 
VALIGN="bottom"
65 
>Chapter 9. HAL Interfaces</TD
66 
><TD
67 
WIDTH="10%"
68 
ALIGN="right"
69 
VALIGN="bottom"
70 
><A
71 
HREF="hal-cache-control.html"
72 
ACCESSKEY="N"
73 
>Next</A
74 
></TD
75 
></TR
76 
></TABLE
77 
><HR
78 
ALIGN="LEFT"
79 
WIDTH="100%"></DIV
80 
><DIV
81 
CLASS="SECTION"
82 
><H1
83 
CLASS="SECTION"
84 
><A
85 
NAME="HAL-INPUT-AND-OUTPUT">HAL I/O</H1
86 
><P
87 
>This section contains definitions for supporting access
88 
to device control registers in an architecture neutral
89 
fashion.</P
90 
><P
91 
>These definitions are normally found in the header file
92 
<TT
93 
CLASS="FILENAME"
94 
>cyg/hal/hal_io.h</TT
95 
>.  This file itself contains
96 
macros that are generic to the architecture. If there are variant or
97 
platform specific IO access macros then these will be found in
98 
<TT
99 
CLASS="FILENAME"
100 
>cyg/hal/var_io.h</TT
101 
> and
102 
<TT
103 
CLASS="FILENAME"
104 
>cyg/hal/plf_io.h</TT
105 
> in the variant or platform HALs
106 
respectively. These files are include automatically by this header, so
107 
need not be included explicitly.</P
108 
><P
109 
>This header (or more likely <TT
110 
CLASS="FILENAME"
111 
>cyg/hal/plf_io.h</TT
112 
>) also
113 
defines the PCI access macros. For more information on these see <A
114 
HREF="pci-library-reference.html"
115 
>the Section called <I
116 
>PCI Library reference</I
117 
> in Chapter 30</A
118 
>.</P
119 
><DIV
120 
CLASS="SECTION"
121 
><H2
122 
CLASS="SECTION"
123 
><A
124 
NAME="AEN8057">Register address</H2
125 
><TABLE
126 
BORDER="5"
127 
BGCOLOR="#E0E0F0"
128 
WIDTH="70%"
129 
><TR
130 
><TD
131 
><PRE
132 
CLASS="PROGRAMLISTING"
133 
>HAL_IO_REGISTER</PRE
134 
></TD
135 
></TR
136 
></TABLE
137 
><P
138 
>This type is used to store the address of an I/O register. It will
139 
normally be a memory address, an integer port address or an offset
140 
into an I/O space. More complex architectures may need to code an
141 
address space plus offset pair into a single word, or may represent it
142 
as a structure.</P
143 
><P
144 
>Values of variables and constants of this type will usually be
145 
supplied by configuration mechanisms or in target specific headers.</P
146 
></DIV
147 
><DIV
148 
CLASS="SECTION"
149 
><H2
150 
CLASS="SECTION"
151 
><A
152 
NAME="AEN8062">Register read</H2
153 
><TABLE
154 
BORDER="5"
155 
BGCOLOR="#E0E0F0"
156 
WIDTH="70%"
157 
><TR
158 
><TD
159 
><PRE
160 
CLASS="PROGRAMLISTING"
161 
>HAL_READ_XXX( register, value )
162 
HAL_READ_XXX_VECTOR( register, buffer, count, stride )</PRE
163 
></TD
164 
></TR
165 
></TABLE
166 
><P
167 
>These macros support the reading of I/O registers in various
168 
sizes. The <TT
169 
CLASS="REPLACEABLE"
170 
><I
171 
>XXX</I
172 
></TT
173 
> component of the name may be
174 
<TT
175 
CLASS="LITERAL"
176 
>UINT8</TT
177 
>, <TT
178 
CLASS="LITERAL"
179 
>UINT16</TT
180 
>,
181 
<TT
182 
CLASS="LITERAL"
183 
>UINT32</TT
184 
>.</P
185 
><P
186 
><TT
187 
CLASS="FUNCTION"
188 
>HAL_READ_XXX()</TT
189 
> reads the appropriately sized
190 
value from the register and stores it in the variable passed as the
191 
second argument.</P
192 
><P
193 
><TT
194 
CLASS="FUNCTION"
195 
>HAL_READ_XXX_VECTOR()</TT
196 
> reads
197 
<TT
198 
CLASS="PARAMETER"
199 
><I
200 
>count</I
201 
></TT
202 
> values of the appropriate size into
203 
<TT
204 
CLASS="PARAMETER"
205 
><I
206 
>buffer</I
207 
></TT
208 
>. The <TT
209 
CLASS="PARAMETER"
210 
><I
211 
>stride</I
212 
></TT
213 
>
214 
controls how the pointer advances through the register space. A stride
215 
of zero will read the same register repeatedly, and a stride of one
216 
will read adjacent registers of the given size. Greater strides will
217 
step by larger amounts, to allow for sparsely mapped registers for
218 
example.</P
219 
></DIV
220 
><DIV
221 
CLASS="SECTION"
222 
><H2
223 
CLASS="SECTION"
224 
><A
225 
NAME="AEN8077">Register write</H2
226 
><TABLE
227 
BORDER="5"
228 
BGCOLOR="#E0E0F0"
229 
WIDTH="70%"
230 
><TR
231 
><TD
232 
><PRE
233 
CLASS="PROGRAMLISTING"
234 
>HAL_WRITE_XXX( register, value )
235 
HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )</PRE
236 
></TD
237 
></TR
238 
></TABLE
239 
><P
240 
>These macros support the writing of I/O registers in various
241 
sizes. The <TT
242 
CLASS="REPLACEABLE"
243 
><I
244 
>XXX</I
245 
></TT
246 
> component of the name may be
247 
<TT
248 
CLASS="LITERAL"
249 
>UINT8</TT
250 
>, <TT
251 
CLASS="LITERAL"
252 
>UINT16</TT
253 
>,
254 
<TT
255 
CLASS="LITERAL"
256 
>UINT32</TT
257 
>.</P
258 
><P
259 
><TT
260 
CLASS="FUNCTION"
261 
>HAL_WRITE_XXX()</TT
262 
> writes
263 
the appropriately sized value from the variable passed as the second argument
264 
stored it in the register.</P
265 
><P
266 
><TT
267 
CLASS="FUNCTION"
268 
>HAL_WRITE_XXX_VECTOR()</TT
269 
> writes
270 
<TT
271 
CLASS="PARAMETER"
272 
><I
273 
>count</I
274 
></TT
275 
> values of the appropriate size from <TT
276 
CLASS="PARAMETER"
277 
><I
278 
>buffer</I
279 
></TT
280 
>. The <TT
281 
CLASS="PARAMETER"
282 
><I
283 
>stride</I
284 
></TT
285 
> controls
286 
how the pointer advances through the register space. A stride of
287 
zero will write the same register repeatedly, and a stride of one
288 
will write adjacent registers of the given size. Greater strides
289 
will step by larger amounts, to allow for sparsely mapped registers
290 
for example.</P
291 
></DIV
292 
></DIV
293 
><DIV
294 
CLASS="NAVFOOTER"
295 
><HR
296 
ALIGN="LEFT"
297 
WIDTH="100%"><TABLE
298 
SUMMARY="Footer navigation table"
299 
WIDTH="100%"
300 
BORDER="0"
301 
CELLPADDING="0"
302 
CELLSPACING="0"
303 
><TR
304 
><TD
305 
WIDTH="33%"
306 
ALIGN="left"
307 
VALIGN="top"
308 
><A
309 
HREF="hal-interrupt-handling.html"
310 
ACCESSKEY="P"
311 
>Prev</A
312 
></TD
313 
><TD
314 
WIDTH="34%"
315 
ALIGN="center"
316 
VALIGN="top"
317 
><A
318 
HREF="ecos-ref.html"
319 
ACCESSKEY="H"
320 
>Home</A
321 
></TD
322 
><TD
323 
WIDTH="33%"
324 
ALIGN="right"
325 
VALIGN="top"
326 
><A
327 
HREF="hal-cache-control.html"
328 
ACCESSKEY="N"
329 
>Next</A
330 
></TD
331 
></TR
332 
><TR
333 
><TD
334 
WIDTH="33%"
335 
ALIGN="left"
336 
VALIGN="top"
337 
>Interrupt Handling</TD
338 
><TD
339 
WIDTH="34%"
340 
ALIGN="center"
341 
VALIGN="top"
342 
><A
343 
HREF="hal-interfaces.html"
344 
ACCESSKEY="U"
345 
>Up</A
346 
></TD
347 
><TD
348 
WIDTH="33%"
349 
ALIGN="right"
350 
VALIGN="top"
351 
>Cache Control</TD
352 
></TR
353 
></TABLE
354 
></DIV
355 
></BODY
356 
></HTML
357 
>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.