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>Variant HAL Porting</TITLE
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>eCos Reference Manual</TH
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><A
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>Prev</A
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></TD
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><TD
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ALIGN="center"
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VALIGN="bottom"
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>Chapter 11. Porting Guide</TD
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><TD
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><DIV
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CLASS="SECTION"
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><H1
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CLASS="SECTION"
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><A
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NAME="HAL-PORTING-VARIANT">Variant HAL Porting</H1
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><P
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>A variant port can be a fairly limited job, but can also
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require quite a lot of work. A variant HAL describes how a specific
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CPU variant differs from the generic CPU architecture. The variant HAL
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can re-define cache, MMU, interrupt, and other features which override
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the default implementation provided by the architecture HAL.</P
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><P
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>Doing a variant port requires a preexisting architecture HAL port. It
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is also likely that a platform port will have to be done at the same
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time if it is to be tested.</P
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN9745">HAL Variant Porting Process</H2
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><P
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>The easiest way to make a new variant HAL is simply to copy an
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existing variant HAL and change all the files to match the new
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variant. If this is the first variant for an architecture, it may be
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hard to decide which parts should be put in the variant - knowledge of
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other variants of the architecture is required.</P
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><P
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>Looking at existing variant HALs (e.g., MIPS tx39, tx49) may be a
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help - usually things such as caching, interrupt and exception
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handling differ between variants. Initialization code, and code for
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handling various core components (FPU, DSP, MMU, etc.) may also differ
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or be missing altogether on some variants. Linker scripts may also require
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specific variant versions.</P
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><DIV
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CLASS="NOTE"
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><BLOCKQUOTE
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CLASS="NOTE"
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><P
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><B
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>Note: </B
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>Some CPU variants may require specific compiler
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support. That support must be in place before you can undertake the
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eCos variant port.</P
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></BLOCKQUOTE
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></DIV
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></DIV
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN9752">HAL Variant CDL</H2
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><P
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>The CDL in a variant HAL tends to depend on the exact functionality
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supported by the variant. If it implements some of the devices
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described in the platform HAL, then the CDL for those will be here
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rather than there (for example the real-time clock).</P
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><P
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>There may also be CDL to select options in the architecture HAL to
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configure it to a particular architectural variant.</P
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><P
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>Each variant needs an entry in the <TT
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CLASS="FILENAME"
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>ecos.db</TT
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>
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file. This is the one for the SH3:</P
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><TABLE
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BORDER="5"
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BGCOLOR="#E0E0F0"
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WIDTH="70%"
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>package CYGPKG_HAL_SH_SH3 {
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    alias         { "SH3 architecture" hal_sh_sh3 }
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    directory     hal/sh/sh3
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    script        hal_sh_sh3.cdl
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    hardware
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    description   "
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        The SH3 (SuperH 3) variant HAL package provides generic
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        support for SH3 variant CPUs."
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}</PRE
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></TD
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></TR
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></TABLE
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><P
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>As you can see, it is very similar to the platform entry.</P
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><P
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>The variant CDL file will contain a package entry named for the
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architecture and variant, matching the package name in the
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<TT
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CLASS="FILENAME"
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>ecos.db</TT
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> file. Here is the initial part of the
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MIPS VR4300 CDL file:</P
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><TABLE
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WIDTH="70%"
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>cdl_package CYGPKG_HAL_MIPS_VR4300 {
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    display       "VR4300 variant"
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    parent        CYGPKG_HAL_MIPS
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    implements    CYGINT_HAL_MIPS_VARIANT
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    hardware
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    include_dir   cyg/hal
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    define_header hal_mips_vr4300.h
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    description   "
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           The VR4300 variant HAL package provides generic support
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           for this processor architecture. It is also necessary to
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           select a specific target platform HAL package."</PRE
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></TD
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></TR
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></TABLE
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><P
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>This defines the package, placing it under the MIPS architecture
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package in the hierarchy. The <TT
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CLASS="LITERAL"
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>implements</TT
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> line
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indicates that this is a MIPS variant. The architecture package uses
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this to check that exactly one variant is configured in.</P
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><P
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>The variant defines some options that cause the architecture HAL to
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configure itself to support this variant.</P
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><TABLE
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>    cdl_option CYGHWR_HAL_MIPS_64BIT {
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        display    "Variant 64 bit architecture support"
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        calculated 1
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    }
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    cdl_option CYGHWR_HAL_MIPS_FPU {
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        display    "Variant FPU support"
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        calculated 1
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    }
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    cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
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        display    "Variant 64 bit FPU support"
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        calculated 1
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    }</PRE
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></TD
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></TR
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></TABLE
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><P
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>These tell the architecture that this is a 64 bit MIPS architecture,
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that it has a floating point unit, and that we are going to use it in
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64 bit mode rather than 32 bit mode.</P
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><P
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>The CDL file finishes off with some build options.</P
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><TABLE
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><PRE
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CLASS="PROGRAMLISTING"
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>    define_proc {
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        puts $::cdl_header "#include &lt;pkgconf/hal_mips.h&gt;"
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    }
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    compile       var_misc.c
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    make {
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        &lt;PREFIX&gt;/lib/target.ld: &lt;PACKAGE&gt;/src/mips_vr4300.ld
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        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $&lt;
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        @echo $@ ": \\" &gt; $(notdir $@).deps
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        @tail +2 target.tmp &gt;&gt; $(notdir $@).deps
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        @echo &gt;&gt; $(notdir $@).deps
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        @rm target.tmp
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    }
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    cdl_option CYGBLD_LINKER_SCRIPT {
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        display "Linker script"
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        flavor data
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        no_define
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        calculated  { "src/mips_vr4300.ld" }
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    }
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}</PRE
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></TD
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></TR
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></TABLE
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><P
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>The <TT
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CLASS="LITERAL"
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>define_proc</TT
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> causes the architecture
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configuration file to be included into the configuration file for the
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variant. The <TT
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CLASS="LITERAL"
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>compile</TT
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> causes the single source file
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for this variant, <TT
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CLASS="FILENAME"
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>var_misc.c</TT
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> to be compiled. The
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<TT
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CLASS="LITERAL"
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>make</TT
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> command emits makefile rules to combine the
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linker script with the <TT
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CLASS="FILENAME"
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>.ldi</TT
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> file to generate
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<TT
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CLASS="LITERAL"
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>target.ld</TT
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>. Finally, in the MIPS HALs, the main
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linker script is defined in the variant, rather than the architecture,
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so <TT
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CLASS="LITERAL"
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>CYGBLD_LINKER_SCRIPT</TT
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> is defined here.</P
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></DIV
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><DIV
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CLASS="SECTION"
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><H2
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CLASS="SECTION"
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><A
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NAME="AEN9778">Cache Support</H2
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><P
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>The main area where the variant is likely to be involved is in cache
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support. Often the only thing that distinguishes one CPU variant from
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another is the size of its caches.</P
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><P
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>In architectures such as the MIPS and PowerPC where cache instructions
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are part of the ISA, most of the actual cache operations are
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implemented in the architecture HAL. In this case the variant HAL only
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needs to define the cache dimensions. The following are the cache
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dimensions defined in the MIPS VR4300 variant
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<TT
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CLASS="FILENAME"
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>var_cache.h</TT
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>.</P
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><TABLE
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BGCOLOR="#E0E0F0"
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><TR
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><TD
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><PRE
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CLASS="PROGRAMLISTING"
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>// Data cache
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#define HAL_DCACHE_SIZE                 (8*1024)        // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE            16              // Size of a data cache line
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#define HAL_DCACHE_WAYS                 1               // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE                 (16*1024)       // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE            32              // Size of a cache line
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#define HAL_ICACHE_WAYS                 1               // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))</PRE
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></TD
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></TR
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></TABLE
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><P
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>Additional cache macros, or overrides for the defaults, may also
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appear in here. While some architectures have instructions for
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managing cache lines, overall enable/disable operations may be handled
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via variant specific registers. If so then
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<TT
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CLASS="FILENAME"
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>var_cache.h</TT
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> should also define the
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<TT
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CLASS="LITERAL"
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>HAL_XCACHE_ENABLE()</TT
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> and
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<TT
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CLASS="LITERAL"
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>HAL_XCACHE_DISABLE()</TT
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> macros.</P
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><P
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>If there are any generic features that the variant does not support
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(cache locking is a typical example) then
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<TT
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CLASS="LITERAL"
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>var_cache.h</TT
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> may need to disable definitions of
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certain operations. It is architecture dependent exactly how this is
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done.</P
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