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<HTML
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><HEAD
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><TITLE
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>Vectors and VSRs</TITLE
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"><LINK
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TITLE="eCos Reference Manual"
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HREF="ecos-ref.html"><LINK
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REL="UP"
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TITLE="Exception Handling"
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HREF="hal-exception-handling.html"><LINK
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REL="PREVIOUS"
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TITLE="Exception Handling"
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HREF="hal-exception-handling.html"><LINK
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TITLE="Default Synchronous Exception Handling"
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>eCos Reference Manual</TH
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WIDTH="80%"
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VALIGN="bottom"
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>Chapter 10. Exception Handling</TD
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><TD
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WIDTH="10%"
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ALIGN="right"
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VALIGN="bottom"
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HREF="hal-default-synchronous-exception-handling.html"
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>Next</A
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></TD
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CLASS="SECTION"
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><A
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NAME="HAL-VECTORS-AND-VSRS">Vectors and VSRs</H1
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><P
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>The CPU delivers all exceptions, whether
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synchronous faults or asynchronous interrupts, to a set of hardware
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defined vectors. Depending on the architecture, these may be
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implemented in a number of different ways. Examples of existing
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mechanisms are:</P
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><P
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></P
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><DIV
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CLASS="VARIABLELIST"
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><DL
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><DT
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>PowerPC</DT
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><DD
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><P
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> Exceptions are vectored to locations 256 bytes apart starting at
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either zero or <TT
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CLASS="LITERAL"
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>0xFFF00000</TT
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>. There are 16 such
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vectors defined by the basic architecture and extra vectors may
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be defined by specific variants. One of the base vectors is for
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all external interrupts, and another is for the architecture
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defined timer.
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</P
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></DD
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><DT
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>MIPS</DT
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><DD
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><P
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> Most exceptions and all interrupts are vectored to a single
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address at either <TT
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CLASS="LITERAL"
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>0x80000000</TT
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> or
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<TT
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CLASS="LITERAL"
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>0xBFC00180</TT
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>. Software is responsible for
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reading the exception code from the CPU <TT
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CLASS="LITERAL"
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>cause</TT
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>
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register to discover its true source. Some TLB and debug
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exceptions are delivered to different vector addresses, but
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these are not used currently by eCos. One of the exception codes
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in the <TT
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CLASS="LITERAL"
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>cause</TT
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> register indicates an external
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interrupt. Additional bits in the <TT
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CLASS="LITERAL"
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>cause</TT
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>
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register provide a first-level decode for the interrupt source,
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one of which represents an architecture defined timer.
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</P
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></DD
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><DT
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>IA32</DT
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><DD
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><P
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> Exceptions are delivered via an Interrupt Descriptor Table (IDT)
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which is essentially an indirection table indexed by exception
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number. The IDT may be placed anywhere in memory. In PC hardware
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the standard interrupt controller can be programmed to deliver
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the external interrupts to a block of 16 vectors at any offset
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in the IDT. There is no hardware supplied mechanism for
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determining the vector taken, other than from the address jumped
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to.
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</P
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></DD
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><DT
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>ARM</DT
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><DD
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><P
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> All exceptions, including the FIQ and IRQ interrupts, are
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vectored to locations four bytes apart starting at zero. There
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is only room for one instruction here, which must immediately
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jump out to handling code higher in memory. Interrupt sources
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have to be decoded entirely from the interrupt controller.
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</P
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></DD
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></DL
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></DIV
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><P
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>With such a wide variety of hardware approaches, it is not possible to
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provide a generic mechanism for the substitution of exception vectors
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directly. Therefore, eCos translates all of these mechanisms in to a
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common approach that can be used by portable code on all platforms.</P
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><P
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>The mechanism implemented is to attach to each hardware vector a short
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piece of trampoline code that makes an indirect jump via a table to
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the actual handler for the exception. This handler is called the
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Vector Service Routine (VSR) and the table is called the VSR table.</P
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><P
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>The trampoline code performs the absolute minimum processing necessary
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to identify the exception source, and jump to the VSR. The VSR is then
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responsible for saving the CPU state and taking the necessary actions
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to handle the exception or interrupt. The entry conditions for the VSR
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are as close to the raw hardware exception entry state as possible -
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although on some platforms the trampoline will have had to move or
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reorganize some registers to do its job.</P
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><P
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>To make this more concrete, consider how the trampoline code operates
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in each of the architectures described above:</P
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><P
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></P
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><DIV
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CLASS="VARIABLELIST"
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><DL
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><DT
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>PowerPC</DT
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><DD
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><P
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> A separate trampoline is contained in each of the vector
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locations. This code saves a few work registers away to the
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special purposes registers available, loads the exception number
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into a register and then uses that to index the VSR table and
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jump to the VSR. The VSR is entered with some registers move to
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the SPRs, and one of the data register containing the number of
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the vector taken.
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</P
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></DD
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><DT
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>MIPS</DT
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><DD
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><P
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> A single trampoline routine attached to the common vector reads
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the exception code out of the <TT
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CLASS="LITERAL"
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>cause</TT
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> register
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and uses that value to index the VSR table and jump to the VSR.
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The trampoline uses the two registers defined in the ABI for
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kernel use to do this, one of these will contain the exception
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vector number for the VSR.
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</P
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></DD
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><DT
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>IA32</DT
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><DD
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><P
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> There is a separate 3 or 4 instruction trampoline pointed to by
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each active IDT table entry. The trampoline for exceptions that
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also have an error code pop it from the stack and put it into a
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memory location. Trampolines for non-error-code exceptions just
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zero the memory location. Then all trampolines push an
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interrupt/exception number onto the stack, and take an indirect
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jump through a precalculated offset in the VSR table. This is
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all done without saving any registers, using memory-only
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operations. The VSR is entered with the vector number pushed
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onto the stack on top of the standard hardware saved state.
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</P
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></DD
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><DT
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>ARM</DT
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><DD
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><P
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> The trampoline consists solely of the single instruction at the
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exception entry point. This is an indirect jump via a location
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32 bytes higher in memory. These locations, from
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<TT
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CLASS="LITERAL"
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>0x20</TT
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> up, form the VSR table. Since each VSR
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is entered in a different CPU mode
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(<TT
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CLASS="LITERAL"
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>SVC,UNDEF,ABORT,IRQ or FIQ</TT
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>) there has to be a
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different VSR for each exception that knows how to save the CPU
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state correctly.
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</P
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></DD
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></DL
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>Exception Handling</TD
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>Default Synchronous Exception Handling</TD
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