OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [iq80310.html] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 unneback 
<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
2 
<!-- This material may be distributed only subject to the terms      -->
3 
<!-- and conditions set forth in the Open Publication License, v1.0  -->
4 
<!-- or later (the latest version is presently available at          -->
5 
<!-- http://www.opencontent.org/openpub/).                           -->
6 
<!-- Distribution of the work or derivative of the work in any       -->
7 
<!-- standard (paper) book form is prohibited unless prior           -->
8 
<!-- permission is obtained from the copyright holder.               -->
9 
<HTML
10 
><HEAD
11 
><TITLE
12 
>ARM/Xscale Cyclone IQ80310</TITLE
13 
><meta name="MSSmartTagsPreventParsing" content="TRUE">
14 
<META
15 
NAME="GENERATOR"
16 
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
17 
"><LINK
18 
REL="HOME"
19 
TITLE="eCos Reference Manual"
20 
HREF="ecos-ref.html"><LINK
21 
REL="UP"
22 
TITLE="Installation and Testing"
23 
HREF="installation-and-testing.html"><LINK
24 
REL="PREVIOUS"
25 
TITLE="ARM/StrongARM(SA11X0) Intrinsyc CerfCube"
26 
HREF="cerfcube.html"><LINK
27 
REL="NEXT"
28 
TITLE="ARM/Xscale Intel IQ80321"
29 
HREF="iq80321.html"></HEAD
30 
><BODY
31 
CLASS="SECT1"
32 
BGCOLOR="#FFFFFF"
33 
TEXT="#000000"
34 
LINK="#0000FF"
35 
VLINK="#840084"
36 
ALINK="#0000FF"
37 
><DIV
38 
CLASS="NAVHEADER"
39 
><TABLE
40 
SUMMARY="Header navigation table"
41 
WIDTH="100%"
42 
BORDER="0"
43 
CELLPADDING="0"
44 
CELLSPACING="0"
45 
><TR
46 
><TH
47 
COLSPAN="3"
48 
ALIGN="center"
49 
>eCos Reference Manual</TH
50 
></TR
51 
><TR
52 
><TD
53 
WIDTH="10%"
54 
ALIGN="left"
55 
VALIGN="bottom"
56 
><A
57 
HREF="cerfcube.html"
58 
ACCESSKEY="P"
59 
>Prev</A
60 
></TD
61 
><TD
62 
WIDTH="80%"
63 
ALIGN="center"
64 
VALIGN="bottom"
65 
>Chapter 5. Installation and Testing</TD
66 
><TD
67 
WIDTH="10%"
68 
ALIGN="right"
69 
VALIGN="bottom"
70 
><A
71 
HREF="iq80321.html"
72 
ACCESSKEY="N"
73 
>Next</A
74 
></TD
75 
></TR
76 
></TABLE
77 
><HR
78 
ALIGN="LEFT"
79 
WIDTH="100%"></DIV
80 
><DIV
81 
CLASS="SECT1"
82 
><H1
83 
CLASS="SECT1"
84 
><A
85 
NAME="IQ80310">ARM/Xscale Cyclone IQ80310</H1
86 
><DIV
87 
CLASS="SECT2"
88 
><H2
89 
CLASS="SECT2"
90 
><A
91 
NAME="AEN6164">Overview</H2
92 
><P
93 
>RedBoot supports
94 
both serial ports and the built-in ethernet port for communication and downloads.
95 
The default serial port settings are 115200,8,N,1. RedBoot also supports flash
96 
management for the onboard 8MB flash.</P
97 
><P
98 
>The following RedBoot configurations are supported:
99 
 
100 
      <DIV
101 
CLASS="INFORMALTABLE"
102 
><A
103 
NAME="AEN6174"><P
104 
></P
105 
><TABLE
106 
BORDER="1"
107 
CLASS="CALSTABLE"
108 
><THEAD
109 
><TR
110 
><TH
111 
ALIGN="LEFT"
112 
VALIGN="TOP"
113 
>Configuration</TH
114 
><TH
115 
ALIGN="LEFT"
116 
VALIGN="TOP"
117 
>Mode</TH
118 
><TH
119 
ALIGN="LEFT"
120 
VALIGN="TOP"
121 
>Description</TH
122 
><TH
123 
ALIGN="LEFT"
124 
VALIGN="TOP"
125 
>File</TH
126 
></TR
127 
></THEAD
128 
><TBODY
129 
><TR
130 
><TD
131 
ALIGN="LEFT"
132 
VALIGN="TOP"
133 
>ROM</TD
134 
><TD
135 
ALIGN="LEFT"
136 
VALIGN="TOP"
137 
>[ROM]</TD
138 
><TD
139 
ALIGN="LEFT"
140 
VALIGN="TOP"
141 
>RedBoot running from the board's flash boot
142 
              sector.</TD
143 
><TD
144 
ALIGN="LEFT"
145 
VALIGN="TOP"
146 
>redboot_ROM.ecm</TD
147 
></TR
148 
><TR
149 
><TD
150 
ALIGN="LEFT"
151 
VALIGN="TOP"
152 
>RAM</TD
153 
><TD
154 
ALIGN="LEFT"
155 
VALIGN="TOP"
156 
>[RAM]</TD
157 
><TD
158 
ALIGN="LEFT"
159 
VALIGN="TOP"
160 
>RedBoot running from RAM with RedBoot in the
161 
              flash boot sector.</TD
162 
><TD
163 
ALIGN="LEFT"
164 
VALIGN="TOP"
165 
>redboot_RAM.ecm</TD
166 
></TR
167 
><TR
168 
><TD
169 
ALIGN="LEFT"
170 
VALIGN="TOP"
171 
>ROMA</TD
172 
><TD
173 
ALIGN="LEFT"
174 
VALIGN="TOP"
175 
>[ROM]</TD
176 
><TD
177 
ALIGN="LEFT"
178 
VALIGN="TOP"
179 
>RedBoot running from flash address 0x40000, with
180 
              ARM bootloader in flash boot sector.</TD
181 
><TD
182 
ALIGN="LEFT"
183 
VALIGN="TOP"
184 
>redboot_ROMA.ecm</TD
185 
></TR
186 
><TR
187 
><TD
188 
ALIGN="LEFT"
189 
VALIGN="TOP"
190 
>RAMA</TD
191 
><TD
192 
ALIGN="LEFT"
193 
VALIGN="TOP"
194 
>[RAM]</TD
195 
><TD
196 
ALIGN="LEFT"
197 
VALIGN="TOP"
198 
>RedBoot running from RAM with ARM bootloader in
199 
              flash boot sector.</TD
200 
><TD
201 
ALIGN="LEFT"
202 
VALIGN="TOP"
203 
>redboot_RAMA.ecm</TD
204 
></TR
205 
></TBODY
206 
></TABLE
207 
><P
208 
></P
209 
></DIV
210 
></P
211 
></DIV
212 
><DIV
213 
CLASS="SECT2"
214 
><H2
215 
CLASS="SECT2"
216 
><A
217 
NAME="AEN6203">Initial Installation Method</H2
218 
><P
219 
>The board manufacturer provides a DOS application which is
220 
capable of programming the flash over the PCI bus, and this is
221 
required for initial installations of RedBoot. Please see the board
222 
manual for information on using this utility.  In general, the process
223 
involves programming one of the two flash based RedBoot images to
224 
flash. The ROM mode RedBoot (which runs from the flash boot sector)
225 
should be programmed to flash address 0x00000000. The ROMA RedBoot
226 
mode (which is started by the ARM bootloader) should be programmed to
227 
flash address 0x00004000.</P
228 
><P
229 
> To install RedBoot to run from the flash boot sector, use the manufacturer's
230 
flash utility to install the ROM mode image at address zero.</P
231 
><P
232 
>To install RedBoot to run from address 0x40000 with the ARM bootloader
233 
in the flash boot sector, use the manufacturer's flash utility to install
234 
the ROMA mode image at address 0x40000. </P
235 
><P
236 
>After booting the initial installation of RedBoot, this warning may
237 
be printed: <TABLE
238 
BORDER="5"
239 
BGCOLOR="#E0E0F0"
240 
WIDTH="70%"
241 
><TR
242 
><TD
243 
><PRE
244 
CLASS="SCREEN"
245 
>flash configuration checksum error or invalid key</PRE
246 
></TD
247 
></TR
248 
></TABLE
249 
>This is normal, and indicates that the flash must be configured
250 
for use by RedBoot. Even if the above message is not printed, it may be a
251 
good idea to reinitialize the flash anyway. Do this with the <B
252 
CLASS="COMMAND"
253 
>fis</B
254 
> command: <TABLE
255 
BORDER="5"
256 
BGCOLOR="#E0E0F0"
257 
WIDTH="70%"
258 
><TR
259 
><TD
260 
><PRE
261 
CLASS="SCREEN"
262 
>RedBoot&#62; <TT
263 
CLASS="USERINPUT"
264 
><B
265 
>fis init</B
266 
></TT
267 
>
268 
About to initialize [format] flash image system - continue (y/n)? <TT
269 
CLASS="USERINPUT"
270 
><B
271 
>y</B
272 
></TT
273 
>
274 
*** Initialize flash Image System
275 
Warning: device contents not erased, some blocks may not be usable
276 
... Unlock from 0x007e0000-0x00800000: .
277 
... Erase from 0x007e0000-0x00800000: .
278 
... Program from 0xa1fd0000-0xa1fd0400 at 0x007e0000: .
279 
... Lock from 0x007e0000-0x00800000: .
280 
Followed by the fconfig command:
281 
   RedBoot&#62; <TT
282 
CLASS="USERINPUT"
283 
><B
284 
>fconfig</B
285 
></TT
286 
>
287 
   Run script at boot: <TT
288 
CLASS="USERINPUT"
289 
><B
290 
>false</B
291 
></TT
292 
>
293 
   Use BOOTP for network configuration: <TT
294 
CLASS="USERINPUT"
295 
><B
296 
>false</B
297 
></TT
298 
>
299 
   Local IP address: <TT
300 
CLASS="USERINPUT"
301 
><B
302 
>192.168.1.153</B
303 
></TT
304 
>
305 
   Default server IP address: <TT
306 
CLASS="USERINPUT"
307 
><B
308 
>192.168.1.10</B
309 
></TT
310 
>
311 
   GDB connection port: <TT
312 
CLASS="USERINPUT"
313 
><B
314 
>1000</B
315 
></TT
316 
>
317 
   Network debug at boot time: <TT
318 
CLASS="USERINPUT"
319 
><B
320 
>false</B
321 
></TT
322 
>
323 
   Update RedBoot non-volatile configuration - continue (y/n)? <TT
324 
CLASS="USERINPUT"
325 
><B
326 
>y</B
327 
></TT
328 
>
329 
   ... Unlock from 0x007c0000-0x007e0000: .
330 
   ... Erase from 0x007c0000-0x007e0000: .
331 
   ... Program from 0xa0013018-0xa0013418 at 0x007c0000: .
332 
   ... Lock from 0x007c0000-0x007e0000: .</PRE
333 
></TD
334 
></TR
335 
></TABLE
336 
></P
337 
><DIV
338 
CLASS="NOTE"
339 
><BLOCKQUOTE
340 
CLASS="NOTE"
341 
><P
342 
><B
343 
>Note: </B
344 
>When later updating RedBoot in situ, it is important to
345 
use a matching ROM and RAM mode pair of images. So use either RAM/ROM
346 
or RAMA/ROMA images. Do not mix them.</P
347 
></BLOCKQUOTE
348 
></DIV
349 
></DIV
350 
><DIV
351 
CLASS="SECT2"
352 
><H2
353 
CLASS="SECT2"
354 
><A
355 
NAME="AEN6224">Error codes</H2
356 
><P
357 
>RedBoot uses the two digit LED display to indicate errors during   board
358 
initialization. Possible error codes are:      <P
359 
CLASS="LITERALLAYOUT"
360 
>88&nbsp;-&nbsp;Unknown&nbsp;Error<br>
361 
55&nbsp;-&nbsp;I2C&nbsp;Error<br>
362 
FF&nbsp;-&nbsp;SDRAM&nbsp;Error<br>
363 
01&nbsp;-&nbsp;No&nbsp;Error</P
364 
></P
365 
></DIV
366 
><DIV
367 
CLASS="SECT2"
368 
><H2
369 
CLASS="SECT2"
370 
><A
371 
NAME="AEN6228">Using RedBoot with ARM Bootloader</H2
372 
><P
373 
>RedBoot can coexist with ARM tools in flash on the IQ80310 board. In
374 
this configuration, the ARM bootloader will occupy the flash boot sector while
375 
RedBoot is located at flash address 0x40000. The sixteen position rotary switch
376 
is used to tell the ARM bootloader to jump to the RedBoot image located at
377 
address 0x40000. RedBoot is selected by switch position 0 or 1. Other switch
378 
positions are used by the ARM firmware and RedBoot will not be started. </P
379 
></DIV
380 
><DIV
381 
CLASS="SECT2"
382 
><H2
383 
CLASS="SECT2"
384 
><A
385 
NAME="AEN6231">Special RedBoot Commands</H2
386 
><P
387 
>A special RedBoot command, <B
388 
CLASS="COMMAND"
389 
>diag</B
390 
>, is used to
391 
access a set of hardware diagnostics provided by the board
392 
manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt:
393 
<TABLE
394 
BORDER="5"
395 
BGCOLOR="#E0E0F0"
396 
WIDTH="70%"
397 
><TR
398 
><TD
399 
><PRE
400 
CLASS="SCREEN"
401 
>RedBoot&#62; <TT
402 
CLASS="USERINPUT"
403 
><B
404 
>diag</B
405 
></TT
406 
>
407 
Entering Hardware Diagnostics - Disabling Data Cache!
408 
1 - Memory Tests
409 
2 - Repeating Memory Tests
410 
3 - 16C552 DUART Serial Port Tests
411 
4 - Rotary Switch S1 Test for positions 0-3
412 
5 - seven Segment LED Tests
413 
6 - Backplane Detection Test
414 
7 - Battery Status Test
415 
8 - External Timer Test
416 
9 - i82559 Ethernet Configuration
417 
10 - i82559 Ethernet Test
418 
11 - Secondary PCI Bus Test
419 
12 - Primary PCI Bus Test
420 
13 - i960Rx/303 PCI Interrupt Test
421 
14 - Internal Timer Test
422 
15 - GPIO Test
423 
 
424 
></TD
425 
></TR
426 
></TABLE
427 
>
428 
Tests for various hardware subsystems are provided, and some
429 
tests require special hardware in order to execute normally. The Ethernet
430 
Configuration item may be used to set the board ethernet address.</P
431 
></DIV
432 
><DIV
433 
CLASS="SECT2"
434 
><H2
435 
CLASS="SECT2"
436 
><A
437 
NAME="AEN6237">IQ80310 Hardware Tests</H2
438 
><P
439 
><TABLE
440 
BORDER="5"
441 
BGCOLOR="#E0E0F0"
442 
WIDTH="70%"
443 
><TR
444 
><TD
445 
><PRE
446 
CLASS="SCREEN"
447 
>1 - Memory Tests
448 
2 - Repeating Memory Tests
449 
3 - 16C552 DUART Serial Port Tests
450 
4 - Rotary Switch S1 Test for positions 0-3
451 
5 - 7 Segment LED Tests
452 
6 - Backplane Detection Test
453 
7 - Battery Status Test
454 
8 - External Timer Test
455 
9 - i82559 Ethernet Configuration
456 
10 - i82559 Ethernet Test
457 
11 - i960Rx/303 PCI Interrupt Test
458 
12 - Internal Timer Test
459 
13 - Secondary PCI Bus Test
460 
14 - Primary PCI Bus Test
461 
15 - Battery Backup SDRAM Memory Test
462 
16 - GPIO Test
463 
17 - Repeat-On-Fail Memory Test
464 
18 - Coyonosa Cache Loop (No return)
465 
19 - Show Software and Hardware Revision
466 
 
467 
Enter the menu item number (0 to quit):  </PRE
468 
></TD
469 
></TR
470 
></TABLE
471 
></P
472 
><P
473 
>Tests for various hardware subsystems are provided, and some tests require
474 
special hardware in order to execute normally. The Ethernet Configuration
475 
item may be used to set the board ethernet address.</P
476 
></DIV
477 
><DIV
478 
CLASS="SECT2"
479 
><H2
480 
CLASS="SECT2"
481 
><A
482 
NAME="AEN6242">Rebuilding RedBoot</H2
483 
><P
484 
>These shell variables provide the platform-specific information
485 
needed for building RedBoot according to the procedure described in
486 
<A
487 
HREF="rebuilding-redboot.html"
488 
>Chapter 3</A
489 
>:
490 
<TABLE
491 
BORDER="5"
492 
BGCOLOR="#E0E0F0"
493 
WIDTH="70%"
494 
><TR
495 
><TD
496 
><PRE
497 
CLASS="PROGRAMLISTING"
498 
>export TARGET=iq80310
499 
export ARCH_DIR=arm
500 
export PLATFORM_DIR=iq80310</PRE
501 
></TD
502 
></TR
503 
></TABLE
504 
></P
505 
><P
506 
>The names of configuration files are listed above with the
507 
description of the associated modes.</P
508 
></DIV
509 
><DIV
510 
CLASS="SECT2"
511 
><H2
512 
CLASS="SECT2"
513 
><A
514 
NAME="AEN6248">Interrupts</H2
515 
><P
516 
>RedBoot uses an interrupt vector table which is located at address 0xA000A004.
517 
Entries in this table are pointers to functions with this protoype::      <TABLE
518 
BORDER="5"
519 
BGCOLOR="#E0E0F0"
520 
WIDTH="70%"
521 
><TR
522 
><TD
523 
><PRE
524 
CLASS="PROGRAMLISTING"
525 
>int irq_handler( unsigned vector, unsigned data )</PRE
526 
></TD
527 
></TR
528 
></TABLE
529 
>On an IQ80310
530 
board, the vector argument is one of 49 interrupts defined in <TT
531 
CLASS="COMPUTEROUTPUT"
532 
>hal/arm/iq80310/current/include/hal_platform_ints.h:</TT
533 
>:   <TABLE
534 
BORDER="5"
535 
BGCOLOR="#E0E0F0"
536 
WIDTH="70%"
537 
><TR
538 
><TD
539 
><PRE
540 
CLASS="PROGRAMLISTING"
541 
>// *** 80200 CPU ***
542 
#define CYGNUM_HAL_INTERRUPT_reserved0     0
543 
#define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.
544 
#define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow
545 
#define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow
546 
#define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit
547 
#define CYGNUM_HAL_INTERRUPT_NIRQ          5 // external IRQ
548 
#define CYGNUM_HAL_INTERRUPT_NFIQ          6 // external FIQ
549 
 
550 
 
551 
// *** XINT6 interrupts ***
552 
#define CYGNUM_HAL_INTERRUPT_DMA_0         7
553 
#define CYGNUM_HAL_INTERRUPT_DMA_1         8
554 
#define CYGNUM_HAL_INTERRUPT_DMA_2         9
555 
#define CYGNUM_HAL_INTERRUPT_GTSC         10 // Global Time Stamp Counter
556 
#define CYGNUM_HAL_INTERRUPT_PEC          11 // Performance Event Counter
557 
#define CYGNUM_HAL_INTERRUPT_AAIP         12 // application accelerator unit
558 
 
559 
 
560 
// *** XINT7 interrupts ***
561 
// I2C interrupts
562 
#define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
563 
#define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL  14
564 
#define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR  15
565 
#define CYGNUM_HAL_INTERRUPT_I2C_STOP     16
566 
#define CYGNUM_HAL_INTERRUPT_I2C_LOSS     17
567 
#define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS  18
568 
 
569 
 
570 
// Messaging Unit interrupts
571 
#define CYGNUM_HAL_INTERRUPT_MESSAGE_0           19
572 
#define CYGNUM_HAL_INTERRUPT_MESSAGE_1           20
573 
#define CYGNUM_HAL_INTERRUPT_DOORBELL            21
574 
#define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL        22
575 
#define CYGNUM_HAL_INTERRUPT_QUEUE_POST          23
576 
#define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24
577 
#define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER      25
578 
// PCI Address Translation Unit
579 
#define CYGNUM_HAL_INTERRUPT_BIST                26
580 
 
581 
 
582 
// *** External board interrupts (XINT3) ***
583 
#define CYGNUM_HAL_INTERRUPT_TIMER        27 // external timer
584 
#define CYGNUM_HAL_INTERRUPT_ETHERNET     28 // onboard enet
585 
#define CYGNUM_HAL_INTERRUPT_SERIAL_A     29 // 16x50 uart A
586 
#define CYGNUM_HAL_INTERRUPT_SERIAL_B     30 // 16x50 uart B
587 
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTD   31 // secondary PCI INTD
588 
// The hardware doesn't (yet?) provide masking or status for these
589 
// even though they can trigger cpu interrupts. ISRs will need to
590 
// poll the device to see if the device actually triggered the
591 
// interrupt.
592 
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTC   32 // secondary PCI INTC
593 
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTB   33 // secondary PCI INTB
594 
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTA   34 // secondary PCI INTA
595 
 
596 
 
597 
// *** NMI Interrupts go to FIQ ***
598 
#define CYGNUM_HAL_INTERRUPT_MCU_ERR       35
599 
#define CYGNUM_HAL_INTERRUPT_PATU_ERR      36
600 
#define CYGNUM_HAL_INTERRUPT_SATU_ERR      37
601 
#define CYGNUM_HAL_INTERRUPT_PBDG_ERR      38
602 
#define CYGNUM_HAL_INTERRUPT_SBDG_ERR      39
603 
#define CYGNUM_HAL_INTERRUPT_DMA0_ERR      40
604 
#define CYGNUM_HAL_INTERRUPT_DMA1_ERR      41
605 
#define CYGNUM_HAL_INTERRUPT_DMA2_ERR      42
606 
#define CYGNUM_HAL_INTERRUPT_MU_ERR        43
607 
#define CYGNUM_HAL_INTERRUPT_reserved52    44
608 
#define CYGNUM_HAL_INTERRUPT_AAU_ERR       45
609 
#define CYGNUM_HAL_INTERRUPT_BIU_ERR       46
610 
 
611 
 
612 
// *** ATU FIQ sources ***
613 
#define CYGNUM_HAL_INTERRUPT_P_SERR        47
614 
#define CYGNUM_HAL_INTERRUPT_S_SERR        48</PRE
615 
></TD
616 
></TR
617 
></TABLE
618 
>The data passed
619 
to the ISR is pulled from a data table <TT
620 
CLASS="COMPUTEROUTPUT"
621 
>(hal_interrupt_data)</TT
622 
> which immediately follows the interrupt vector table. With
623 
49 interrupts, the data table starts at address 0xA000A0C8.   </P
624 
><P
625 
>An application may create a normal C function with the above prototype
626 
to be an ISR. Just poke its address into the table at the correct index and
627 
enable the interrupt at its source. The return value of the ISR is ignored
628 
by RedBoot.</P
629 
></DIV
630 
><DIV
631 
CLASS="SECT2"
632 
><H2
633 
CLASS="SECT2"
634 
><A
635 
NAME="AEN6256">Memory Maps</H2
636 
><P
637 
>The first level page table is located at 0xa0004000. Two second level
638 
tables are also used. One second level table is located at 0xa0008000 and
639 
maps the first 1MB of flash. The other second level table is at 0xa0008400,
640 
and maps the first 1MB of SDRAM. <DIV
641 
CLASS="NOTE"
642 
><BLOCKQUOTE
643 
CLASS="NOTE"
644 
><P
645 
><B
646 
>NOTE: </B
647 
>The virtual memory maps in this section use a C and B column to indicate
648 
whether or not the region is cached (C) or buffered (B).</P
649 
></BLOCKQUOTE
650 
></DIV
651 
></P
652 
><P
653 
><TABLE
654 
BORDER="5"
655 
BGCOLOR="#E0E0F0"
656 
WIDTH="70%"
657 
><TR
658 
><TD
659 
><PRE
660 
CLASS="PROGRAMLISTING"
661 
>Physical Address Range     Description
662 
-----------------------    ----------------------------------
663 
0x00000000 - 0x00000fff    flash Memory
664 
0x00001000 - 0x00001fff    80312 Internal Registers
665 
0x00002000 - 0x007fffff    flash Memory
666 
0x00800000 - 0x7fffffff    PCI ATU Outbound Direct Window
667 
0x80000000 - 0x83ffffff    Primary PCI 32-bit Memory
668 
0x84000000 - 0x87ffffff    Primary PCI 64-bit Memory
669 
0x88000000 - 0x8bffffff    Secondary PCI 32-bit Memory
670 
0x8c000000 - 0x8fffffff    Secondary PCI 64-bit Memory
671 
0x90000000 - 0x9000ffff    Primary PCI IO Space
672 
0x90010000 - 0x9001ffff    Secondary PCI IO Space
673 
0x90020000 - 0x9fffffff    Unused
674 
0xa0000000 - 0xbfffffff    SDRAM
675 
0xc0000000 - 0xefffffff    Unused
676 
0xf0000000 - 0xffffffff    80200 Internal Registers
677 
 
678 
 
679 
Virtual Address Range    C B  Description
680 
-----------------------  - -  ----------------------------------
681 
0x00000000 - 0x00000fff  Y Y  SDRAM
682 
0x00001000 - 0x00001fff  N N  80312 Internal Registers
683 
0x00002000 - 0x007fffff  Y N  flash Memory
684 
0x00800000 - 0x7fffffff  N N  PCI ATU Outbound Direct Window
685 
0x80000000 - 0x83ffffff  N N  Primary PCI 32-bit Memory
686 
0x84000000 - 0x87ffffff  N N  Primary PCI 64-bit Memory
687 
0x88000000 - 0x8bffffff  N N  Secondary PCI 32-bit Memory
688 
0x8c000000 - 0x8fffffff  N N  Secondary PCI 64-bit Memory
689 
0x90000000 - 0x9000ffff  N N  Primary PCI IO Space
690 
0x90010000 - 0x9001ffff  N N  Secondary PCI IO Space
691 
0xa0000000 - 0xbfffffff  Y Y  SDRAM
692 
0xc0000000 - 0xcfffffff  Y Y  Cache Flush Region
693 
0xd0000000 - 0xd0000fff  Y N  first 4k page of flash
694 
0xf0000000 - 0xffffffff  N N  80200 Internal Registers </PRE
695 
></TD
696 
></TR
697 
></TABLE
698 
></P
699 
></DIV
700 
><DIV
701 
CLASS="SECT2"
702 
><H2
703 
CLASS="SECT2"
704 
><A
705 
NAME="AEN6264">Platform Resource Usage</H2
706 
><P
707 
>The external timer is used as a polled timer to provide timeout support
708 
for networking and XModem file transfers.</P
709 
></DIV
710 
></DIV
711 
><DIV
712 
CLASS="NAVFOOTER"
713 
><HR
714 
ALIGN="LEFT"
715 
WIDTH="100%"><TABLE
716 
SUMMARY="Footer navigation table"
717 
WIDTH="100%"
718 
BORDER="0"
719 
CELLPADDING="0"
720 
CELLSPACING="0"
721 
><TR
722 
><TD
723 
WIDTH="33%"
724 
ALIGN="left"
725 
VALIGN="top"
726 
><A
727 
HREF="cerfcube.html"
728 
ACCESSKEY="P"
729 
>Prev</A
730 
></TD
731 
><TD
732 
WIDTH="34%"
733 
ALIGN="center"
734 
VALIGN="top"
735 
><A
736 
HREF="ecos-ref.html"
737 
ACCESSKEY="H"
738 
>Home</A
739 
></TD
740 
><TD
741 
WIDTH="33%"
742 
ALIGN="right"
743 
VALIGN="top"
744 
><A
745 
HREF="iq80321.html"
746 
ACCESSKEY="N"
747 
>Next</A
748 
></TD
749 
></TR
750 
><TR
751 
><TD
752 
WIDTH="33%"
753 
ALIGN="left"
754 
VALIGN="top"
755 
>ARM/StrongARM(SA11X0) Intrinsyc CerfCube</TD
756 
><TD
757 
WIDTH="34%"
758 
ALIGN="center"
759 
VALIGN="top"
760 
><A
761 
HREF="installation-and-testing.html"
762 
ACCESSKEY="U"
763 
>Up</A
764 
></TD
765 
><TD
766 
WIDTH="33%"
767 
ALIGN="right"
768 
VALIGN="top"
769 
>ARM/Xscale Intel IQ80321</TD
770 
></TR
771 
></TABLE
772 
></DIV
773 
></BODY
774 
></HTML
775 
>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.