| 1 |
28 |
unneback |
<!-- Copyright (C) 2003 Red Hat, Inc. -->
|
| 2 |
|
|
<!-- This material may be distributed only subject to the terms -->
|
| 3 |
|
|
<!-- and conditions set forth in the Open Publication License, v1.0 -->
|
| 4 |
|
|
<!-- or later (the latest version is presently available at -->
|
| 5 |
|
|
<!-- http://www.opencontent.org/openpub/). -->
|
| 6 |
|
|
<!-- Distribution of the work or derivative of the work in any -->
|
| 7 |
|
|
<!-- standard (paper) book form is prohibited unless prior -->
|
| 8 |
|
|
<!-- permission is obtained from the copyright holder. -->
|
| 9 |
|
|
<HTML
|
| 10 |
|
|
><HEAD
|
| 11 |
|
|
><TITLE
|
| 12 |
|
|
>ARM/Xscale Intel IQ80321</TITLE
|
| 13 |
|
|
><meta name="MSSmartTagsPreventParsing" content="TRUE">
|
| 14 |
|
|
<META
|
| 15 |
|
|
NAME="GENERATOR"
|
| 16 |
|
|
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
|
| 17 |
|
|
"><LINK
|
| 18 |
|
|
REL="HOME"
|
| 19 |
|
|
TITLE="eCos Reference Manual"
|
| 20 |
|
|
HREF="ecos-ref.html"><LINK
|
| 21 |
|
|
REL="UP"
|
| 22 |
|
|
TITLE="Installation and Testing"
|
| 23 |
|
|
HREF="installation-and-testing.html"><LINK
|
| 24 |
|
|
REL="PREVIOUS"
|
| 25 |
|
|
TITLE="ARM/Xscale Cyclone IQ80310"
|
| 26 |
|
|
HREF="iq80310.html"><LINK
|
| 27 |
|
|
REL="NEXT"
|
| 28 |
|
|
TITLE="CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board "
|
| 29 |
|
|
HREF="calmrisc16.html"></HEAD
|
| 30 |
|
|
><BODY
|
| 31 |
|
|
CLASS="SECT1"
|
| 32 |
|
|
BGCOLOR="#FFFFFF"
|
| 33 |
|
|
TEXT="#000000"
|
| 34 |
|
|
LINK="#0000FF"
|
| 35 |
|
|
VLINK="#840084"
|
| 36 |
|
|
ALINK="#0000FF"
|
| 37 |
|
|
><DIV
|
| 38 |
|
|
CLASS="NAVHEADER"
|
| 39 |
|
|
><TABLE
|
| 40 |
|
|
SUMMARY="Header navigation table"
|
| 41 |
|
|
WIDTH="100%"
|
| 42 |
|
|
BORDER="0"
|
| 43 |
|
|
CELLPADDING="0"
|
| 44 |
|
|
CELLSPACING="0"
|
| 45 |
|
|
><TR
|
| 46 |
|
|
><TH
|
| 47 |
|
|
COLSPAN="3"
|
| 48 |
|
|
ALIGN="center"
|
| 49 |
|
|
>eCos Reference Manual</TH
|
| 50 |
|
|
></TR
|
| 51 |
|
|
><TR
|
| 52 |
|
|
><TD
|
| 53 |
|
|
WIDTH="10%"
|
| 54 |
|
|
ALIGN="left"
|
| 55 |
|
|
VALIGN="bottom"
|
| 56 |
|
|
><A
|
| 57 |
|
|
HREF="iq80310.html"
|
| 58 |
|
|
ACCESSKEY="P"
|
| 59 |
|
|
>Prev</A
|
| 60 |
|
|
></TD
|
| 61 |
|
|
><TD
|
| 62 |
|
|
WIDTH="80%"
|
| 63 |
|
|
ALIGN="center"
|
| 64 |
|
|
VALIGN="bottom"
|
| 65 |
|
|
>Chapter 5. Installation and Testing</TD
|
| 66 |
|
|
><TD
|
| 67 |
|
|
WIDTH="10%"
|
| 68 |
|
|
ALIGN="right"
|
| 69 |
|
|
VALIGN="bottom"
|
| 70 |
|
|
><A
|
| 71 |
|
|
HREF="calmrisc16.html"
|
| 72 |
|
|
ACCESSKEY="N"
|
| 73 |
|
|
>Next</A
|
| 74 |
|
|
></TD
|
| 75 |
|
|
></TR
|
| 76 |
|
|
></TABLE
|
| 77 |
|
|
><HR
|
| 78 |
|
|
ALIGN="LEFT"
|
| 79 |
|
|
WIDTH="100%"></DIV
|
| 80 |
|
|
><DIV
|
| 81 |
|
|
CLASS="SECT1"
|
| 82 |
|
|
><H1
|
| 83 |
|
|
CLASS="SECT1"
|
| 84 |
|
|
><A
|
| 85 |
|
|
NAME="IQ80321">ARM/Xscale Intel IQ80321</H1
|
| 86 |
|
|
><DIV
|
| 87 |
|
|
CLASS="SECT2"
|
| 88 |
|
|
><H2
|
| 89 |
|
|
CLASS="SECT2"
|
| 90 |
|
|
><A
|
| 91 |
|
|
NAME="AEN6269">Overview</H2
|
| 92 |
|
|
><P
|
| 93 |
|
|
>RedBoot supports
|
| 94 |
|
|
the serial port and the built-in ethernet port for communication and downloads.
|
| 95 |
|
|
The default serial port settings are 115200,8,N,1. RedBoot also supports flash
|
| 96 |
|
|
management for the onboard 8MB flash.</P
|
| 97 |
|
|
><P
|
| 98 |
|
|
>The following RedBoot configurations are supported:
|
| 99 |
|
|
|
| 100 |
|
|
<DIV
|
| 101 |
|
|
CLASS="INFORMALTABLE"
|
| 102 |
|
|
><A
|
| 103 |
|
|
NAME="AEN6279"><P
|
| 104 |
|
|
></P
|
| 105 |
|
|
><TABLE
|
| 106 |
|
|
BORDER="1"
|
| 107 |
|
|
CLASS="CALSTABLE"
|
| 108 |
|
|
><THEAD
|
| 109 |
|
|
><TR
|
| 110 |
|
|
><TH
|
| 111 |
|
|
ALIGN="LEFT"
|
| 112 |
|
|
VALIGN="TOP"
|
| 113 |
|
|
>Configuration</TH
|
| 114 |
|
|
><TH
|
| 115 |
|
|
ALIGN="LEFT"
|
| 116 |
|
|
VALIGN="TOP"
|
| 117 |
|
|
>Mode</TH
|
| 118 |
|
|
><TH
|
| 119 |
|
|
ALIGN="LEFT"
|
| 120 |
|
|
VALIGN="TOP"
|
| 121 |
|
|
>Description</TH
|
| 122 |
|
|
><TH
|
| 123 |
|
|
ALIGN="LEFT"
|
| 124 |
|
|
VALIGN="TOP"
|
| 125 |
|
|
>File</TH
|
| 126 |
|
|
></TR
|
| 127 |
|
|
></THEAD
|
| 128 |
|
|
><TBODY
|
| 129 |
|
|
><TR
|
| 130 |
|
|
><TD
|
| 131 |
|
|
ALIGN="LEFT"
|
| 132 |
|
|
VALIGN="TOP"
|
| 133 |
|
|
>ROM</TD
|
| 134 |
|
|
><TD
|
| 135 |
|
|
ALIGN="LEFT"
|
| 136 |
|
|
VALIGN="TOP"
|
| 137 |
|
|
>[ROM]</TD
|
| 138 |
|
|
><TD
|
| 139 |
|
|
ALIGN="LEFT"
|
| 140 |
|
|
VALIGN="TOP"
|
| 141 |
|
|
>RedBoot running from the board's flash boot
|
| 142 |
|
|
sector.</TD
|
| 143 |
|
|
><TD
|
| 144 |
|
|
ALIGN="LEFT"
|
| 145 |
|
|
VALIGN="TOP"
|
| 146 |
|
|
>redboot_ROM.ecm</TD
|
| 147 |
|
|
></TR
|
| 148 |
|
|
><TR
|
| 149 |
|
|
><TD
|
| 150 |
|
|
ALIGN="LEFT"
|
| 151 |
|
|
VALIGN="TOP"
|
| 152 |
|
|
>RAM</TD
|
| 153 |
|
|
><TD
|
| 154 |
|
|
ALIGN="LEFT"
|
| 155 |
|
|
VALIGN="TOP"
|
| 156 |
|
|
>[RAM]</TD
|
| 157 |
|
|
><TD
|
| 158 |
|
|
ALIGN="LEFT"
|
| 159 |
|
|
VALIGN="TOP"
|
| 160 |
|
|
>RedBoot running from RAM with RedBoot in the
|
| 161 |
|
|
flash boot sector.</TD
|
| 162 |
|
|
><TD
|
| 163 |
|
|
ALIGN="LEFT"
|
| 164 |
|
|
VALIGN="TOP"
|
| 165 |
|
|
>redboot_RAM.ecm</TD
|
| 166 |
|
|
></TR
|
| 167 |
|
|
></TBODY
|
| 168 |
|
|
></TABLE
|
| 169 |
|
|
><P
|
| 170 |
|
|
></P
|
| 171 |
|
|
></DIV
|
| 172 |
|
|
></P
|
| 173 |
|
|
></DIV
|
| 174 |
|
|
><DIV
|
| 175 |
|
|
CLASS="SECT2"
|
| 176 |
|
|
><H2
|
| 177 |
|
|
CLASS="SECT2"
|
| 178 |
|
|
><A
|
| 179 |
|
|
NAME="AEN6298">Initial Installation Method</H2
|
| 180 |
|
|
><P
|
| 181 |
|
|
>The board manufacturer provides a DOS application which is capable of
|
| 182 |
|
|
programming the flash over the PCI bus, and this is required for initial installations
|
| 183 |
|
|
of RedBoot. Please see the board manual for information on using this utility.
|
| 184 |
|
|
In general, the process involves programming the ROM mode RedBoot
|
| 185 |
|
|
image to flash. RedBoot should be programmed to flash address
|
| 186 |
|
|
0x00000000 using the DOS utility.</P
|
| 187 |
|
|
><P
|
| 188 |
|
|
>After booting the initial installation of RedBoot, this warning may
|
| 189 |
|
|
be printed: <TABLE
|
| 190 |
|
|
BORDER="5"
|
| 191 |
|
|
BGCOLOR="#E0E0F0"
|
| 192 |
|
|
WIDTH="70%"
|
| 193 |
|
|
><TR
|
| 194 |
|
|
><TD
|
| 195 |
|
|
><PRE
|
| 196 |
|
|
CLASS="SCREEN"
|
| 197 |
|
|
>flash configuration checksum error or invalid key</PRE
|
| 198 |
|
|
></TD
|
| 199 |
|
|
></TR
|
| 200 |
|
|
></TABLE
|
| 201 |
|
|
>This is normal, and indicates that the flash must be configured
|
| 202 |
|
|
for use by RedBoot. Even if the above message is not printed, it may be a
|
| 203 |
|
|
good idea to reinitialize the flash anyway. Do this with the <B
|
| 204 |
|
|
CLASS="COMMAND"
|
| 205 |
|
|
>fis</B
|
| 206 |
|
|
> command: <TABLE
|
| 207 |
|
|
BORDER="5"
|
| 208 |
|
|
BGCOLOR="#E0E0F0"
|
| 209 |
|
|
WIDTH="70%"
|
| 210 |
|
|
><TR
|
| 211 |
|
|
><TD
|
| 212 |
|
|
><PRE
|
| 213 |
|
|
CLASS="SCREEN"
|
| 214 |
|
|
>RedBoot> <TT
|
| 215 |
|
|
CLASS="USERINPUT"
|
| 216 |
|
|
><B
|
| 217 |
|
|
>fis init</B
|
| 218 |
|
|
></TT
|
| 219 |
|
|
>
|
| 220 |
|
|
About to initialize [format] FLASH image system - continue (y/n)? <TT
|
| 221 |
|
|
CLASS="USERINPUT"
|
| 222 |
|
|
><B
|
| 223 |
|
|
>y</B
|
| 224 |
|
|
></TT
|
| 225 |
|
|
>
|
| 226 |
|
|
*** Initialize FLASH Image System
|
| 227 |
|
|
Warning: device contents not erased, some blocks may not be usable
|
| 228 |
|
|
... Unlock from 0xf07e0000-0xf0800000: .
|
| 229 |
|
|
... Erase from 0xf07e0000-0xf0800000: .
|
| 230 |
|
|
... Program from 0x01ddf000-0x01ddf400 at 0xf07e0000: .
|
| 231 |
|
|
... Lock from 0xf07e0000-0xf0800000: .</PRE
|
| 232 |
|
|
></TD
|
| 233 |
|
|
></TR
|
| 234 |
|
|
></TABLE
|
| 235 |
|
|
></P
|
| 236 |
|
|
></DIV
|
| 237 |
|
|
><DIV
|
| 238 |
|
|
CLASS="SECT2"
|
| 239 |
|
|
><H2
|
| 240 |
|
|
CLASS="SECT2"
|
| 241 |
|
|
><A
|
| 242 |
|
|
NAME="AEN6307">Switch Settings</H2
|
| 243 |
|
|
><P
|
| 244 |
|
|
>The 80321 board is highly configurable through a number of switches and jumpers.
|
| 245 |
|
|
RedBoot makes some assumptions about board configuration and attention must be paid
|
| 246 |
|
|
to these assumptions for reliable RedBoot operation:
|
| 247 |
|
|
<P
|
| 248 |
|
|
></P
|
| 249 |
|
|
><UL
|
| 250 |
|
|
><LI
|
| 251 |
|
|
><P
|
| 252 |
|
|
>The onboard ethernet and the secondary slot may be placed in a
|
| 253 |
|
|
private space so that they are not seen by a PC BIOS. If the board is to be used
|
| 254 |
|
|
in a PC with BIOS, then the ethernet should be placed in this private space so that
|
| 255 |
|
|
RedBoot and the BIOS do not conflict.</P
|
| 256 |
|
|
></LI
|
| 257 |
|
|
><LI
|
| 258 |
|
|
><P
|
| 259 |
|
|
>RedBoot assumes that the board is plugged into a PC with BIOS. This
|
| 260 |
|
|
requires RedBoot to detect when the BIOS has configured the PCI-X secondary bus. If
|
| 261 |
|
|
the board is placed in a backplane, RedBoot will never see the BIOS configure the
|
| 262 |
|
|
secondary bus. To prevent this wait, set switch S7E1-3 to ON when using the board
|
| 263 |
|
|
in a backplane.</P
|
| 264 |
|
|
></LI
|
| 265 |
|
|
><LI
|
| 266 |
|
|
><P
|
| 267 |
|
|
>For the remaining switch settings, the following is a known good
|
| 268 |
|
|
configuration:
|
| 269 |
|
|
<DIV
|
| 270 |
|
|
CLASS="INFORMALTABLE"
|
| 271 |
|
|
><A
|
| 272 |
|
|
NAME="AEN6317"><P
|
| 273 |
|
|
></P
|
| 274 |
|
|
><TABLE
|
| 275 |
|
|
BORDER="1"
|
| 276 |
|
|
CLASS="CALSTABLE"
|
| 277 |
|
|
><TBODY
|
| 278 |
|
|
><TR
|
| 279 |
|
|
><TD
|
| 280 |
|
|
ALIGN="LEFT"
|
| 281 |
|
|
VALIGN="TOP"
|
| 282 |
|
|
>S1D1</TD
|
| 283 |
|
|
><TD
|
| 284 |
|
|
ALIGN="LEFT"
|
| 285 |
|
|
VALIGN="TOP"
|
| 286 |
|
|
>All OFF</TD
|
| 287 |
|
|
></TR
|
| 288 |
|
|
><TR
|
| 289 |
|
|
><TD
|
| 290 |
|
|
ALIGN="LEFT"
|
| 291 |
|
|
VALIGN="TOP"
|
| 292 |
|
|
>S7E1</TD
|
| 293 |
|
|
><TD
|
| 294 |
|
|
ALIGN="LEFT"
|
| 295 |
|
|
VALIGN="TOP"
|
| 296 |
|
|
>7 is ON, all others OFF</TD
|
| 297 |
|
|
></TR
|
| 298 |
|
|
><TR
|
| 299 |
|
|
><TD
|
| 300 |
|
|
ALIGN="LEFT"
|
| 301 |
|
|
VALIGN="TOP"
|
| 302 |
|
|
>S8E1</TD
|
| 303 |
|
|
><TD
|
| 304 |
|
|
ALIGN="LEFT"
|
| 305 |
|
|
VALIGN="TOP"
|
| 306 |
|
|
>2,3,5,6 are ON, all others OFF</TD
|
| 307 |
|
|
></TR
|
| 308 |
|
|
><TR
|
| 309 |
|
|
><TD
|
| 310 |
|
|
ALIGN="LEFT"
|
| 311 |
|
|
VALIGN="TOP"
|
| 312 |
|
|
>S8E2</TD
|
| 313 |
|
|
><TD
|
| 314 |
|
|
ALIGN="LEFT"
|
| 315 |
|
|
VALIGN="TOP"
|
| 316 |
|
|
>2,3 are ON, all others OFF</TD
|
| 317 |
|
|
></TR
|
| 318 |
|
|
><TR
|
| 319 |
|
|
><TD
|
| 320 |
|
|
ALIGN="LEFT"
|
| 321 |
|
|
VALIGN="TOP"
|
| 322 |
|
|
>S9E1</TD
|
| 323 |
|
|
><TD
|
| 324 |
|
|
ALIGN="LEFT"
|
| 325 |
|
|
VALIGN="TOP"
|
| 326 |
|
|
>3 is ON, all others OFF</TD
|
| 327 |
|
|
></TR
|
| 328 |
|
|
><TR
|
| 329 |
|
|
><TD
|
| 330 |
|
|
ALIGN="LEFT"
|
| 331 |
|
|
VALIGN="TOP"
|
| 332 |
|
|
>S4D1</TD
|
| 333 |
|
|
><TD
|
| 334 |
|
|
ALIGN="LEFT"
|
| 335 |
|
|
VALIGN="TOP"
|
| 336 |
|
|
>1,3 are ON, all others OFF</TD
|
| 337 |
|
|
></TR
|
| 338 |
|
|
><TR
|
| 339 |
|
|
><TD
|
| 340 |
|
|
ALIGN="LEFT"
|
| 341 |
|
|
VALIGN="TOP"
|
| 342 |
|
|
>J9E1</TD
|
| 343 |
|
|
><TD
|
| 344 |
|
|
ALIGN="LEFT"
|
| 345 |
|
|
VALIGN="TOP"
|
| 346 |
|
|
>2,3 jumpered</TD
|
| 347 |
|
|
></TR
|
| 348 |
|
|
><TR
|
| 349 |
|
|
><TD
|
| 350 |
|
|
ALIGN="LEFT"
|
| 351 |
|
|
VALIGN="TOP"
|
| 352 |
|
|
>J9F1</TD
|
| 353 |
|
|
><TD
|
| 354 |
|
|
ALIGN="LEFT"
|
| 355 |
|
|
VALIGN="TOP"
|
| 356 |
|
|
>2,3 jumpered</TD
|
| 357 |
|
|
></TR
|
| 358 |
|
|
><TR
|
| 359 |
|
|
><TD
|
| 360 |
|
|
ALIGN="LEFT"
|
| 361 |
|
|
VALIGN="TOP"
|
| 362 |
|
|
>J3F1</TD
|
| 363 |
|
|
><TD
|
| 364 |
|
|
ALIGN="LEFT"
|
| 365 |
|
|
VALIGN="TOP"
|
| 366 |
|
|
>Nothing jumpered</TD
|
| 367 |
|
|
></TR
|
| 368 |
|
|
><TR
|
| 369 |
|
|
><TD
|
| 370 |
|
|
ALIGN="LEFT"
|
| 371 |
|
|
VALIGN="TOP"
|
| 372 |
|
|
>J3G1</TD
|
| 373 |
|
|
><TD
|
| 374 |
|
|
ALIGN="LEFT"
|
| 375 |
|
|
VALIGN="TOP"
|
| 376 |
|
|
>2,3 jumpered</TD
|
| 377 |
|
|
></TR
|
| 378 |
|
|
><TR
|
| 379 |
|
|
><TD
|
| 380 |
|
|
ALIGN="LEFT"
|
| 381 |
|
|
VALIGN="TOP"
|
| 382 |
|
|
>J1G2</TD
|
| 383 |
|
|
><TD
|
| 384 |
|
|
ALIGN="LEFT"
|
| 385 |
|
|
VALIGN="TOP"
|
| 386 |
|
|
>2,3 jumpered</TD
|
| 387 |
|
|
></TR
|
| 388 |
|
|
></TBODY
|
| 389 |
|
|
></TABLE
|
| 390 |
|
|
><P
|
| 391 |
|
|
></P
|
| 392 |
|
|
></DIV
|
| 393 |
|
|
></P
|
| 394 |
|
|
></LI
|
| 395 |
|
|
></UL
|
| 396 |
|
|
></P
|
| 397 |
|
|
></DIV
|
| 398 |
|
|
><DIV
|
| 399 |
|
|
CLASS="SECT2"
|
| 400 |
|
|
><H2
|
| 401 |
|
|
CLASS="SECT2"
|
| 402 |
|
|
><A
|
| 403 |
|
|
NAME="AEN6353">LED Codes</H2
|
| 404 |
|
|
><P
|
| 405 |
|
|
>RedBoot uses the two digit LED display to indicate status during board
|
| 406 |
|
|
initialization. Possible codes are:</P
|
| 407 |
|
|
><P
|
| 408 |
|
|
CLASS="LITERALLAYOUT"
|
| 409 |
|
|
>LED Actions<br>
|
| 410 |
|
|
-------------------------------------------------------------<br>
|
| 411 |
|
|
Power-On/Reset<br>
|
| 412 |
|
|
88<br>
|
| 413 |
|
|
Set the CPSR<br>
|
| 414 |
|
|
Enable coprocessor access<br>
|
| 415 |
|
|
Drain write and fill buffer<br>
|
| 416 |
|
|
Setup PBIU chip selects<br>
|
| 417 |
|
|
A1<br>
|
| 418 |
|
|
Enable the Icache<br>
|
| 419 |
|
|
A2<br>
|
| 420 |
|
|
Move FLASH chip select from 0x0 to 0xF0000000<br>
|
| 421 |
|
|
Jump to new FLASH location<br>
|
| 422 |
|
|
A3<br>
|
| 423 |
|
|
Setup and enable the MMU<br>
|
| 424 |
|
|
A4<br>
|
| 425 |
|
|
I2C interface initialization<br>
|
| 426 |
|
|
90<br>
|
| 427 |
|
|
Wait for I2C initialization to complete<br>
|
| 428 |
|
|
91<br>
|
| 429 |
|
|
Send address (via I2C) to the DIMM<br>
|
| 430 |
|
|
92<br>
|
| 431 |
|
|
Wait for transmit complete<br>
|
| 432 |
|
|
93<br>
|
| 433 |
|
|
Read SDRAM PD data from DIMM<br>
|
| 434 |
|
|
94<br>
|
| 435 |
|
|
Read remainder of EEPROM data.<br>
|
| 436 |
|
|
An error will result in one of the following<br>
|
| 437 |
|
|
error codes on the LEDs:<br>
|
| 438 |
|
|
77 BAD EEPROM checksum<br>
|
| 439 |
|
|
55 I2C protocol error<br>
|
| 440 |
|
|
FF bank size error<br>
|
| 441 |
|
|
A5<br>
|
| 442 |
|
|
Setup DDR memory interface<br>
|
| 443 |
|
|
A6<br>
|
| 444 |
|
|
Enable branch target buffer<br>
|
| 445 |
|
|
Drain the write & fill buffers<br>
|
| 446 |
|
|
Flush Icache, Dcache and BTB<br>
|
| 447 |
|
|
Flush instuction and data TLBs<br>
|
| 448 |
|
|
Drain the write & fill buffers<br>
|
| 449 |
|
|
SL<br>
|
| 450 |
|
|
ECC Scrub Loop<br>
|
| 451 |
|
|
SE<br>
|
| 452 |
|
|
A7<br>
|
| 453 |
|
|
Clean, drain, flush the main Dcache<br>
|
| 454 |
|
|
A8<br>
|
| 455 |
|
|
Clean, drain, flush the mini Dcache<br>
|
| 456 |
|
|
Flush Dcache<br>
|
| 457 |
|
|
Drain the write & fill buffers<br>
|
| 458 |
|
|
A9<br>
|
| 459 |
|
|
Enable ECC<br>
|
| 460 |
|
|
AA<br>
|
| 461 |
|
|
Save SDRAM size<br>
|
| 462 |
|
|
Move MMU tables into RAM<br>
|
| 463 |
|
|
AB<br>
|
| 464 |
|
|
Clean, drain, flush the main Dcache<br>
|
| 465 |
|
|
Clean, drain, flush the mini Dcache<br>
|
| 466 |
|
|
Drain the write & fill buffers<br>
|
| 467 |
|
|
AC<br>
|
| 468 |
|
|
Set the TTB register to DRAM mmu_table<br>
|
| 469 |
|
|
AD<br>
|
| 470 |
|
|
Set mode to IRQ mode<br>
|
| 471 |
|
|
A7<br>
|
| 472 |
|
|
Move SWI & Undefined "vectors" to RAM (at 0x0)<br>
|
| 473 |
|
|
A6<br>
|
| 474 |
|
|
Switch to supervisor mode<br>
|
| 475 |
|
|
A5<br>
|
| 476 |
|
|
Move remaining "vectors" to RAM (at 0x0)<br>
|
| 477 |
|
|
A4<br>
|
| 478 |
|
|
Copy DATA to RAM<br>
|
| 479 |
|
|
Initialize interrupt exception environment<br>
|
| 480 |
|
|
Initialize stack<br>
|
| 481 |
|
|
Clear BSS section<br>
|
| 482 |
|
|
A3<br>
|
| 483 |
|
|
Call platform specific hardware initialization<br>
|
| 484 |
|
|
A2<br>
|
| 485 |
|
|
Run through static constructors<br>
|
| 486 |
|
|
A1<br>
|
| 487 |
|
|
Start up the eCos kernel or RedBoot</P
|
| 488 |
|
|
></DIV
|
| 489 |
|
|
><DIV
|
| 490 |
|
|
CLASS="SECT2"
|
| 491 |
|
|
><H2
|
| 492 |
|
|
CLASS="SECT2"
|
| 493 |
|
|
><A
|
| 494 |
|
|
NAME="AEN6357">Special RedBoot Commands</H2
|
| 495 |
|
|
><P
|
| 496 |
|
|
>A special RedBoot command, <B
|
| 497 |
|
|
CLASS="COMMAND"
|
| 498 |
|
|
>diag</B
|
| 499 |
|
|
>, is used to
|
| 500 |
|
|
access a set of hardware diagnostics. To access the diagnostic menu,
|
| 501 |
|
|
enter <B
|
| 502 |
|
|
CLASS="COMMAND"
|
| 503 |
|
|
>diag</B
|
| 504 |
|
|
> at the RedBoot prompt:
|
| 505 |
|
|
<TABLE
|
| 506 |
|
|
BORDER="5"
|
| 507 |
|
|
BGCOLOR="#E0E0F0"
|
| 508 |
|
|
WIDTH="70%"
|
| 509 |
|
|
><TR
|
| 510 |
|
|
><TD
|
| 511 |
|
|
><PRE
|
| 512 |
|
|
CLASS="SCREEN"
|
| 513 |
|
|
>RedBoot> <TT
|
| 514 |
|
|
CLASS="USERINPUT"
|
| 515 |
|
|
><B
|
| 516 |
|
|
>diag</B
|
| 517 |
|
|
></TT
|
| 518 |
|
|
>
|
| 519 |
|
|
Entering Hardware Diagnostics - Disabling Data Cache!
|
| 520 |
|
|
|
| 521 |
|
|
IQ80321 Hardware Tests
|
| 522 |
|
|
|
| 523 |
|
|
1 - Memory Tests
|
| 524 |
|
|
2 - Repeating Memory Tests
|
| 525 |
|
|
3 - Repeat-On-Fail Memory Tests
|
| 526 |
|
|
4 - Rotary Switch S1 Test
|
| 527 |
|
|
5 - 7 Segment LED Tests
|
| 528 |
|
|
6 - i82544 Ethernet Configuration
|
| 529 |
|
|
7 - Baterry Status Test
|
| 530 |
|
|
8 - Battery Backup SDRAM Memory Test
|
| 531 |
|
|
9 - Timer Test
|
| 532 |
|
|
10 - PCI Bus test
|
| 533 |
|
|
11 - CPU Cache Loop (No Return)
|
| 534 |
|
|
|
| 535 |
|
|
Enter the menu item number (0 to quit):</PRE
|
| 536 |
|
|
></TD
|
| 537 |
|
|
></TR
|
| 538 |
|
|
></TABLE
|
| 539 |
|
|
>
|
| 540 |
|
|
Tests for various hardware subsystems are provided, and some tests require
|
| 541 |
|
|
special hardware in order to execute normally. The Ethernet Configuration
|
| 542 |
|
|
item may be used to set the board ethernet address.</P
|
| 543 |
|
|
><DIV
|
| 544 |
|
|
CLASS="SECT3"
|
| 545 |
|
|
><H3
|
| 546 |
|
|
CLASS="SECT3"
|
| 547 |
|
|
><A
|
| 548 |
|
|
NAME="AEN6364">Memory Tests</H3
|
| 549 |
|
|
><P
|
| 550 |
|
|
>This test is used to test installed DDR SDRAM memory. Five different
|
| 551 |
|
|
tests are run over the given address ranges. If errors are encountered, the
|
| 552 |
|
|
test is aborted and information about the failure is printed. When selected,
|
| 553 |
|
|
the user will be prompted to enter the base address of the test range and its
|
| 554 |
|
|
size. The numbers must be in hex with no leading “0x”</P
|
| 555 |
|
|
><TABLE
|
| 556 |
|
|
BORDER="5"
|
| 557 |
|
|
BGCOLOR="#E0E0F0"
|
| 558 |
|
|
WIDTH="70%"
|
| 559 |
|
|
><TR
|
| 560 |
|
|
><TD
|
| 561 |
|
|
><PRE
|
| 562 |
|
|
CLASS="SCREEN"
|
| 563 |
|
|
>Enter the menu item number (0 to quit): <TT
|
| 564 |
|
|
CLASS="USERINPUT"
|
| 565 |
|
|
><B
|
| 566 |
|
|
>1</B
|
| 567 |
|
|
></TT
|
| 568 |
|
|
>
|
| 569 |
|
|
|
| 570 |
|
|
Base address of memory to test (in hex): <TT
|
| 571 |
|
|
CLASS="USERINPUT"
|
| 572 |
|
|
><B
|
| 573 |
|
|
>100000</B
|
| 574 |
|
|
></TT
|
| 575 |
|
|
>
|
| 576 |
|
|
|
| 577 |
|
|
Size of memory to test (in hex): <TT
|
| 578 |
|
|
CLASS="USERINPUT"
|
| 579 |
|
|
><B
|
| 580 |
|
|
>200000</B
|
| 581 |
|
|
></TT
|
| 582 |
|
|
>
|
| 583 |
|
|
|
| 584 |
|
|
Testing memory from 0x00100000 to 0x002fffff.
|
| 585 |
|
|
|
| 586 |
|
|
Walking 1's test:
|
| 587 |
|
|
0000000100000002000000040000000800000010000000200000004000000080
|
| 588 |
|
|
0000010000000200000004000000080000001000000020000000400000008000
|
| 589 |
|
|
0001000000020000000400000008000000100000002000000040000000800000
|
| 590 |
|
|
0100000002000000040000000800000010000000200000004000000080000000
|
| 591 |
|
|
passed
|
| 592 |
|
|
32-bit address test: passed
|
| 593 |
|
|
32-bit address bar test: passed
|
| 594 |
|
|
8-bit address test: passed
|
| 595 |
|
|
Byte address bar test: passed
|
| 596 |
|
|
Memory test done.</PRE
|
| 597 |
|
|
></TD
|
| 598 |
|
|
></TR
|
| 599 |
|
|
></TABLE
|
| 600 |
|
|
></DIV
|
| 601 |
|
|
><DIV
|
| 602 |
|
|
CLASS="SECT3"
|
| 603 |
|
|
><H3
|
| 604 |
|
|
CLASS="SECT3"
|
| 605 |
|
|
><A
|
| 606 |
|
|
NAME="AEN6371">Repeating Memory Tests</H3
|
| 607 |
|
|
><P
|
| 608 |
|
|
>The repeating memory tests are exactly the same as the above memory tests,
|
| 609 |
|
|
except that the tests are automatically rerun after completion. The only way out
|
| 610 |
|
|
of this test is to reset the board.</P
|
| 611 |
|
|
></DIV
|
| 612 |
|
|
><DIV
|
| 613 |
|
|
CLASS="SECT3"
|
| 614 |
|
|
><H3
|
| 615 |
|
|
CLASS="SECT3"
|
| 616 |
|
|
><A
|
| 617 |
|
|
NAME="AEN6374">Repeat-On-Fail Memory Tests</H3
|
| 618 |
|
|
><P
|
| 619 |
|
|
>This is similar to the repeating memory tests except that when an error
|
| 620 |
|
|
is found, the failing test continuously retries on the failing address.</P
|
| 621 |
|
|
></DIV
|
| 622 |
|
|
><DIV
|
| 623 |
|
|
CLASS="SECT3"
|
| 624 |
|
|
><H3
|
| 625 |
|
|
CLASS="SECT3"
|
| 626 |
|
|
><A
|
| 627 |
|
|
NAME="AEN6377">Rotary Switch S1 Test</H3
|
| 628 |
|
|
><P
|
| 629 |
|
|
>This tests the operation of the sixteen position rotary switch. When run,
|
| 630 |
|
|
this test will display the current position of the rotary switch on the LED
|
| 631 |
|
|
display. Slowly dial through each position and confirm reading on LED.</P
|
| 632 |
|
|
></DIV
|
| 633 |
|
|
><DIV
|
| 634 |
|
|
CLASS="SECT3"
|
| 635 |
|
|
><H3
|
| 636 |
|
|
CLASS="SECT3"
|
| 637 |
|
|
><A
|
| 638 |
|
|
NAME="AEN6380">7 Segment LED Tests</H3
|
| 639 |
|
|
><P
|
| 640 |
|
|
>This tests the operation of the seven segment displays. When run, each
|
| 641 |
|
|
LED cycles through 0 through F and a decimal point.</P
|
| 642 |
|
|
></DIV
|
| 643 |
|
|
><DIV
|
| 644 |
|
|
CLASS="SECT3"
|
| 645 |
|
|
><H3
|
| 646 |
|
|
CLASS="SECT3"
|
| 647 |
|
|
><A
|
| 648 |
|
|
NAME="AEN6383">i82544 Ethernet Configuration</H3
|
| 649 |
|
|
><P
|
| 650 |
|
|
>This test initializes the ethernet controller’s serial EEPROM if
|
| 651 |
|
|
the current contents are invalid. In any case, this test will also allow the
|
| 652 |
|
|
user to enter a six byte ethernet MAC address into the serial EEPROM.</P
|
| 653 |
|
|
><TABLE
|
| 654 |
|
|
BORDER="5"
|
| 655 |
|
|
BGCOLOR="#E0E0F0"
|
| 656 |
|
|
WIDTH="70%"
|
| 657 |
|
|
><TR
|
| 658 |
|
|
><TD
|
| 659 |
|
|
><PRE
|
| 660 |
|
|
CLASS="SCREEN"
|
| 661 |
|
|
>Enter the menu item number (0 to quit): <TT
|
| 662 |
|
|
CLASS="USERINPUT"
|
| 663 |
|
|
><B
|
| 664 |
|
|
>6</B
|
| 665 |
|
|
></TT
|
| 666 |
|
|
>
|
| 667 |
|
|
|
| 668 |
|
|
|
| 669 |
|
|
Current MAC address: 00:80:4d:46:00:02
|
| 670 |
|
|
Enter desired MAC address: <TT
|
| 671 |
|
|
CLASS="USERINPUT"
|
| 672 |
|
|
><B
|
| 673 |
|
|
>00:80:4d:46:00:01</B
|
| 674 |
|
|
></TT
|
| 675 |
|
|
>
|
| 676 |
|
|
Writing to the Serial EEPROM... Done
|
| 677 |
|
|
|
| 678 |
|
|
******** Reset The Board To Have Changes Take Effect ********</PRE
|
| 679 |
|
|
></TD
|
| 680 |
|
|
></TR
|
| 681 |
|
|
></TABLE
|
| 682 |
|
|
></DIV
|
| 683 |
|
|
><DIV
|
| 684 |
|
|
CLASS="SECT3"
|
| 685 |
|
|
><H3
|
| 686 |
|
|
CLASS="SECT3"
|
| 687 |
|
|
><A
|
| 688 |
|
|
NAME="AEN6389">Battery Status Test</H3
|
| 689 |
|
|
><P
|
| 690 |
|
|
>This tests the current status of the battery. First, the test checks to
|
| 691 |
|
|
see if the battery is installed and reports that finding. If the battery is
|
| 692 |
|
|
installed, the test further determines whether the battery status is one or
|
| 693 |
|
|
more of the following:
|
| 694 |
|
|
<P
|
| 695 |
|
|
></P
|
| 696 |
|
|
><UL
|
| 697 |
|
|
><LI
|
| 698 |
|
|
><P
|
| 699 |
|
|
>Battery is charging.</P
|
| 700 |
|
|
></LI
|
| 701 |
|
|
><LI
|
| 702 |
|
|
><P
|
| 703 |
|
|
>Battery is fully discharged.</P
|
| 704 |
|
|
></LI
|
| 705 |
|
|
><LI
|
| 706 |
|
|
><P
|
| 707 |
|
|
>Battery voltage measures within normal operating range.</P
|
| 708 |
|
|
></LI
|
| 709 |
|
|
></UL
|
| 710 |
|
|
></P
|
| 711 |
|
|
></DIV
|
| 712 |
|
|
><DIV
|
| 713 |
|
|
CLASS="SECT3"
|
| 714 |
|
|
><H3
|
| 715 |
|
|
CLASS="SECT3"
|
| 716 |
|
|
><A
|
| 717 |
|
|
NAME="AEN6399">Battery Backup SDRAM Memory Test</H3
|
| 718 |
|
|
><P
|
| 719 |
|
|
>This tests the battery backup of SDRAM memory. This test is a three
|
| 720 |
|
|
step process:</P
|
| 721 |
|
|
><P
|
| 722 |
|
|
></P
|
| 723 |
|
|
><OL
|
| 724 |
|
|
TYPE="1"
|
| 725 |
|
|
><LI
|
| 726 |
|
|
><P
|
| 727 |
|
|
>Select Battery backup test from main diag menu, then write
|
| 728 |
|
|
data to SDRAM.</P
|
| 729 |
|
|
></LI
|
| 730 |
|
|
><LI
|
| 731 |
|
|
><P
|
| 732 |
|
|
>Turn off power for 60 seconds, then repower the board.</P
|
| 733 |
|
|
></LI
|
| 734 |
|
|
><LI
|
| 735 |
|
|
><P
|
| 736 |
|
|
>Select Battery backup test from main diag menu, then check
|
| 737 |
|
|
data that was written in step 1.</P
|
| 738 |
|
|
></LI
|
| 739 |
|
|
></OL
|
| 740 |
|
|
></DIV
|
| 741 |
|
|
><DIV
|
| 742 |
|
|
CLASS="SECT3"
|
| 743 |
|
|
><H3
|
| 744 |
|
|
CLASS="SECT3"
|
| 745 |
|
|
><A
|
| 746 |
|
|
NAME="AEN6409">Timer Test</H3
|
| 747 |
|
|
><P
|
| 748 |
|
|
>This tests the internal timer by printing a number of dots at one
|
| 749 |
|
|
second intervals.</P
|
| 750 |
|
|
></DIV
|
| 751 |
|
|
><DIV
|
| 752 |
|
|
CLASS="SECT3"
|
| 753 |
|
|
><H3
|
| 754 |
|
|
CLASS="SECT3"
|
| 755 |
|
|
><A
|
| 756 |
|
|
NAME="AEN6412">PCI Bus Test</H3
|
| 757 |
|
|
><P
|
| 758 |
|
|
>This tests the secondary PCI-X bus and socket. This test requires that
|
| 759 |
|
|
an IQ80310 board be plugged into the secondary slot of the IOP80321 board.
|
| 760 |
|
|
The test assumes at least 32MB of installed memory on the IQ80310. That memory
|
| 761 |
|
|
is mapped into the IOP80321 address space and the memory tests are run on that
|
| 762 |
|
|
memory.</P
|
| 763 |
|
|
></DIV
|
| 764 |
|
|
><DIV
|
| 765 |
|
|
CLASS="SECT3"
|
| 766 |
|
|
><H3
|
| 767 |
|
|
CLASS="SECT3"
|
| 768 |
|
|
><A
|
| 769 |
|
|
NAME="AEN6415">CPU Cache Loop</H3
|
| 770 |
|
|
><P
|
| 771 |
|
|
>This test puts the CPU into a tight loop run entirely from the ICache.
|
| 772 |
|
|
This should prevent all external bus accesses.</P
|
| 773 |
|
|
></DIV
|
| 774 |
|
|
></DIV
|
| 775 |
|
|
><DIV
|
| 776 |
|
|
CLASS="SECT2"
|
| 777 |
|
|
><H2
|
| 778 |
|
|
CLASS="SECT2"
|
| 779 |
|
|
><A
|
| 780 |
|
|
NAME="AEN6418">Rebuilding RedBoot</H2
|
| 781 |
|
|
><P
|
| 782 |
|
|
>These shell variables provide the platform-specific information
|
| 783 |
|
|
needed for building RedBoot according to the procedure described in
|
| 784 |
|
|
<A
|
| 785 |
|
|
HREF="rebuilding-redboot.html"
|
| 786 |
|
|
>Chapter 3</A
|
| 787 |
|
|
>:
|
| 788 |
|
|
<TABLE
|
| 789 |
|
|
BORDER="5"
|
| 790 |
|
|
BGCOLOR="#E0E0F0"
|
| 791 |
|
|
WIDTH="70%"
|
| 792 |
|
|
><TR
|
| 793 |
|
|
><TD
|
| 794 |
|
|
><PRE
|
| 795 |
|
|
CLASS="PROGRAMLISTING"
|
| 796 |
|
|
>export TARGET=iq80321
|
| 797 |
|
|
export ARCH_DIR=arm
|
| 798 |
|
|
export PLATFORM_DIR=xscale/iq80321</PRE
|
| 799 |
|
|
></TD
|
| 800 |
|
|
></TR
|
| 801 |
|
|
></TABLE
|
| 802 |
|
|
></P
|
| 803 |
|
|
><P
|
| 804 |
|
|
>The names of configuration files are listed above with the
|
| 805 |
|
|
description of the associated modes.</P
|
| 806 |
|
|
></DIV
|
| 807 |
|
|
><DIV
|
| 808 |
|
|
CLASS="SECT2"
|
| 809 |
|
|
><H2
|
| 810 |
|
|
CLASS="SECT2"
|
| 811 |
|
|
><A
|
| 812 |
|
|
NAME="AEN6424">Interrupts</H2
|
| 813 |
|
|
><P
|
| 814 |
|
|
>RedBoot uses an interrupt vector table which is located at address 0x8004.
|
| 815 |
|
|
Entries in this table are pointers to functions with this protoype:: <TABLE
|
| 816 |
|
|
BORDER="5"
|
| 817 |
|
|
BGCOLOR="#E0E0F0"
|
| 818 |
|
|
WIDTH="70%"
|
| 819 |
|
|
><TR
|
| 820 |
|
|
><TD
|
| 821 |
|
|
><PRE
|
| 822 |
|
|
CLASS="PROGRAMLISTING"
|
| 823 |
|
|
>int irq_handler( unsigned vector, unsigned data )</PRE
|
| 824 |
|
|
></TD
|
| 825 |
|
|
></TR
|
| 826 |
|
|
></TABLE
|
| 827 |
|
|
>On an IQ80321
|
| 828 |
|
|
board, the vector argument is one of 32 interrupts defined in <TT
|
| 829 |
|
|
CLASS="COMPUTEROUTPUT"
|
| 830 |
|
|
>hal/arm/xscale/verde/current/include/hal_var_ints.h:</TT
|
| 831 |
|
|
>: <TABLE
|
| 832 |
|
|
BORDER="5"
|
| 833 |
|
|
BGCOLOR="#E0E0F0"
|
| 834 |
|
|
WIDTH="70%"
|
| 835 |
|
|
><TR
|
| 836 |
|
|
><TD
|
| 837 |
|
|
><PRE
|
| 838 |
|
|
CLASS="PROGRAMLISTING"
|
| 839 |
|
|
>// *** 80200 CPU ***
|
| 840 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA0_EOT 0
|
| 841 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA0_EOC 1
|
| 842 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA1_EOT 2
|
| 843 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA1_EOC 3
|
| 844 |
|
|
#define CYGNUM_HAL_INTERRUPT_RSVD_4 4
|
| 845 |
|
|
#define CYGNUM_HAL_INTERRUPT_RSVD_5 5
|
| 846 |
|
|
#define CYGNUM_HAL_INTERRUPT_AA_EOT 6
|
| 847 |
|
|
#define CYGNUM_HAL_INTERRUPT_AA_EOC 7
|
| 848 |
|
|
#define CYGNUM_HAL_INTERRUPT_CORE_PMON 8
|
| 849 |
|
|
#define CYGNUM_HAL_INTERRUPT_TIMER0 9
|
| 850 |
|
|
#define CYGNUM_HAL_INTERRUPT_TIMER1 10
|
| 851 |
|
|
#define CYGNUM_HAL_INTERRUPT_I2C_0 11
|
| 852 |
|
|
#define CYGNUM_HAL_INTERRUPT_I2C_1 12
|
| 853 |
|
|
#define CYGNUM_HAL_INTERRUPT_MESSAGING 13
|
| 854 |
|
|
#define CYGNUM_HAL_INTERRUPT_ATU_BIST 14
|
| 855 |
|
|
#define CYGNUM_HAL_INTERRUPT_PERFMON 15
|
| 856 |
|
|
#define CYGNUM_HAL_INTERRUPT_CORE_PMU 16
|
| 857 |
|
|
#define CYGNUM_HAL_INTERRUPT_BIU_ERR 17
|
| 858 |
|
|
#define CYGNUM_HAL_INTERRUPT_ATU_ERR 18
|
| 859 |
|
|
#define CYGNUM_HAL_INTERRUPT_MCU_ERR 19
|
| 860 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA0_ERR 20
|
| 861 |
|
|
#define CYGNUM_HAL_INTERRUPT_DMA1_ERR 22
|
| 862 |
|
|
#define CYGNUM_HAL_INTERRUPT_AA_ERR 23
|
| 863 |
|
|
#define CYGNUM_HAL_INTERRUPT_MSG_ERR 24
|
| 864 |
|
|
#define CYGNUM_HAL_INTERRUPT_SSP 25
|
| 865 |
|
|
#define CYGNUM_HAL_INTERRUPT_RSVD_26 26
|
| 866 |
|
|
#define CYGNUM_HAL_INTERRUPT_XINT0 27
|
| 867 |
|
|
#define CYGNUM_HAL_INTERRUPT_XINT1 28
|
| 868 |
|
|
#define CYGNUM_HAL_INTERRUPT_XINT2 29
|
| 869 |
|
|
#define CYGNUM_HAL_INTERRUPT_XINT3 30
|
| 870 |
|
|
#define CYGNUM_HAL_INTERRUPT_HPI 31</PRE
|
| 871 |
|
|
></TD
|
| 872 |
|
|
></TR
|
| 873 |
|
|
></TABLE
|
| 874 |
|
|
>
|
| 875 |
|
|
The data passed to the ISR is pulled from a data table <TT
|
| 876 |
|
|
CLASS="COMPUTEROUTPUT"
|
| 877 |
|
|
>(hal_interrupt_data)</TT
|
| 878 |
|
|
> which immediately follows the interrupt vector table. With
|
| 879 |
|
|
32 interrupts, the data table starts at address 0x8084. </P
|
| 880 |
|
|
><P
|
| 881 |
|
|
>An application may create a normal C function with the above prototype
|
| 882 |
|
|
to be an ISR. Just poke its address into the table at the correct index and
|
| 883 |
|
|
enable the interrupt at its source. The return value of the ISR is ignored
|
| 884 |
|
|
by RedBoot.</P
|
| 885 |
|
|
></DIV
|
| 886 |
|
|
><DIV
|
| 887 |
|
|
CLASS="SECT2"
|
| 888 |
|
|
><H2
|
| 889 |
|
|
CLASS="SECT2"
|
| 890 |
|
|
><A
|
| 891 |
|
|
NAME="AEN6432">Memory Maps</H2
|
| 892 |
|
|
><P
|
| 893 |
|
|
>The RAM based page table is located at RAM start + 0x4000. RedBoot may be configured
|
| 894 |
|
|
for one of two memory maps. The difference between them is the location of RAM and the
|
| 895 |
|
|
PCI outbound windows. The alternative memory map may be used when
|
| 896 |
|
|
building RedBoot or eCos by using the <TT
|
| 897 |
|
|
CLASS="LITERAL"
|
| 898 |
|
|
>RAM_ALTMAP</TT
|
| 899 |
|
|
>
|
| 900 |
|
|
and <TT
|
| 901 |
|
|
CLASS="LITERAL"
|
| 902 |
|
|
>ROM_ALTMAP</TT
|
| 903 |
|
|
> startup types in the configuration.
|
| 904 |
|
|
<DIV
|
| 905 |
|
|
CLASS="NOTE"
|
| 906 |
|
|
><BLOCKQUOTE
|
| 907 |
|
|
CLASS="NOTE"
|
| 908 |
|
|
><P
|
| 909 |
|
|
><B
|
| 910 |
|
|
>NOTE: </B
|
| 911 |
|
|
>The virtual memory maps in this section use a C, B, and X column to indicate
|
| 912 |
|
|
the caching policy for the region..</P
|
| 913 |
|
|
></BLOCKQUOTE
|
| 914 |
|
|
></DIV
|
| 915 |
|
|
></P
|
| 916 |
|
|
><P
|
| 917 |
|
|
><TABLE
|
| 918 |
|
|
BORDER="5"
|
| 919 |
|
|
BGCOLOR="#E0E0F0"
|
| 920 |
|
|
WIDTH="70%"
|
| 921 |
|
|
><TR
|
| 922 |
|
|
><TD
|
| 923 |
|
|
><PRE
|
| 924 |
|
|
CLASS="PROGRAMLISTING"
|
| 925 |
|
|
>X C B Description
|
| 926 |
|
|
- - - ---------------------------------------------
|
| 927 |
|
|
|
| 928 |
|
|
|
| 929 |
|
|
|
| 930 |
|
|
|
| 931 |
|
|
1 0 0 Invalid -- not used
|
| 932 |
|
|
1 0 1 Uncached/Buffered No write buffer coalescing
|
| 933 |
|
|
1 1 0 Mini DCache - Policy set by Aux Ctl Register
|
| 934 |
|
|
1 1 1 Cached/Buffered Write Back, Read/Write Allocate
|
| 935 |
|
|
|
| 936 |
|
|
Physical Address Range Description
|
| 937 |
|
|
----------------------- ----------------------------------
|
| 938 |
|
|
0x00000000 - 0x7fffffff ATU Outbound Direct Window
|
| 939 |
|
|
0x80000000 - 0x900fffff ATU Outbound Translate Windows
|
| 940 |
|
|
0xa0000000 - 0xbfffffff SDRAM
|
| 941 |
|
|
0xf0000000 - 0xf0800000 FLASH (PBIU CS0)
|
| 942 |
|
|
0xfe800000 - 0xfe800fff UART (PBIU CS1)
|
| 943 |
|
|
0xfe840000 - 0xfe840fff Left 7-segment LED (PBIU CS3)
|
| 944 |
|
|
0xfe850000 - 0xfe850fff Right 7-segment LED (PBIU CS2)
|
| 945 |
|
|
0xfe8d0000 - 0xfe8d0fff Rotary Switch (PBIU CS4)
|
| 946 |
|
|
0xfe8f0000 - 0xfe8f0fff Baterry Status (PBIU CS5)
|
| 947 |
|
|
0xfff00000 - 0xffffffff Verde Memory mapped Registers
|
| 948 |
|
|
|
| 949 |
|
|
|
| 950 |
|
|
Default Virtual Map X C B Description
|
| 951 |
|
|
----------------------- - - - ----------------------------------
|
| 952 |
|
|
0x00000000 - 0x1fffffff 1 1 1 SDRAM
|
| 953 |
|
|
0x20000000 - 0x9fffffff 0 0 0 ATU Outbound Direct Window
|
| 954 |
|
|
0xa0000000 - 0xb00fffff 0 0 0 ATU Outbound Translate Windows
|
| 955 |
|
|
0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM
|
| 956 |
|
|
0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem)
|
| 957 |
|
|
0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0)
|
| 958 |
|
|
0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1)
|
| 959 |
|
|
0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3)
|
| 960 |
|
|
0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2)
|
| 961 |
|
|
0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4)
|
| 962 |
|
|
0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5)
|
| 963 |
|
|
0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers
|
| 964 |
|
|
|
| 965 |
|
|
Alternate Virtual Map X C B Description
|
| 966 |
|
|
----------------------- - - - ----------------------------------
|
| 967 |
|
|
0x00000000 - 0x000fffff 1 1 1 Alias for 1st MB of SDRAM
|
| 968 |
|
|
0x00100000 - 0x7fffffff 0 0 0 ATU Outbound Direct Window
|
| 969 |
|
|
0x80000000 - 0x900fffff 0 0 0 ATU Outbound Translate Windows
|
| 970 |
|
|
0xa0000000 - 0xbfffffff 1 1 1 SDRAM
|
| 971 |
|
|
0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM
|
| 972 |
|
|
0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem)
|
| 973 |
|
|
0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0)
|
| 974 |
|
|
0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1)
|
| 975 |
|
|
0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3)
|
| 976 |
|
|
0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2)
|
| 977 |
|
|
0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4)
|
| 978 |
|
|
0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5)
|
| 979 |
|
|
0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers </PRE
|
| 980 |
|
|
></TD
|
| 981 |
|
|
></TR
|
| 982 |
|
|
></TABLE
|
| 983 |
|
|
></P
|
| 984 |
|
|
></DIV
|
| 985 |
|
|
><DIV
|
| 986 |
|
|
CLASS="SECT2"
|
| 987 |
|
|
><H2
|
| 988 |
|
|
CLASS="SECT2"
|
| 989 |
|
|
><A
|
| 990 |
|
|
NAME="AEN6442">Platform Resource Usage</H2
|
| 991 |
|
|
><P
|
| 992 |
|
|
>The Verde programmable timer0 is used for timeout support
|
| 993 |
|
|
for networking and XModem file transfers.</P
|
| 994 |
|
|
></DIV
|
| 995 |
|
|
></DIV
|
| 996 |
|
|
><DIV
|
| 997 |
|
|
CLASS="NAVFOOTER"
|
| 998 |
|
|
><HR
|
| 999 |
|
|
ALIGN="LEFT"
|
| 1000 |
|
|
WIDTH="100%"><TABLE
|
| 1001 |
|
|
SUMMARY="Footer navigation table"
|
| 1002 |
|
|
WIDTH="100%"
|
| 1003 |
|
|
BORDER="0"
|
| 1004 |
|
|
CELLPADDING="0"
|
| 1005 |
|
|
CELLSPACING="0"
|
| 1006 |
|
|
><TR
|
| 1007 |
|
|
><TD
|
| 1008 |
|
|
WIDTH="33%"
|
| 1009 |
|
|
ALIGN="left"
|
| 1010 |
|
|
VALIGN="top"
|
| 1011 |
|
|
><A
|
| 1012 |
|
|
HREF="iq80310.html"
|
| 1013 |
|
|
ACCESSKEY="P"
|
| 1014 |
|
|
>Prev</A
|
| 1015 |
|
|
></TD
|
| 1016 |
|
|
><TD
|
| 1017 |
|
|
WIDTH="34%"
|
| 1018 |
|
|
ALIGN="center"
|
| 1019 |
|
|
VALIGN="top"
|
| 1020 |
|
|
><A
|
| 1021 |
|
|
HREF="ecos-ref.html"
|
| 1022 |
|
|
ACCESSKEY="H"
|
| 1023 |
|
|
>Home</A
|
| 1024 |
|
|
></TD
|
| 1025 |
|
|
><TD
|
| 1026 |
|
|
WIDTH="33%"
|
| 1027 |
|
|
ALIGN="right"
|
| 1028 |
|
|
VALIGN="top"
|
| 1029 |
|
|
><A
|
| 1030 |
|
|
HREF="calmrisc16.html"
|
| 1031 |
|
|
ACCESSKEY="N"
|
| 1032 |
|
|
>Next</A
|
| 1033 |
|
|
></TD
|
| 1034 |
|
|
></TR
|
| 1035 |
|
|
><TR
|
| 1036 |
|
|
><TD
|
| 1037 |
|
|
WIDTH="33%"
|
| 1038 |
|
|
ALIGN="left"
|
| 1039 |
|
|
VALIGN="top"
|
| 1040 |
|
|
>ARM/Xscale Cyclone IQ80310</TD
|
| 1041 |
|
|
><TD
|
| 1042 |
|
|
WIDTH="34%"
|
| 1043 |
|
|
ALIGN="center"
|
| 1044 |
|
|
VALIGN="top"
|
| 1045 |
|
|
><A
|
| 1046 |
|
|
HREF="installation-and-testing.html"
|
| 1047 |
|
|
ACCESSKEY="U"
|
| 1048 |
|
|
>Up</A
|
| 1049 |
|
|
></TD
|
| 1050 |
|
|
><TD
|
| 1051 |
|
|
WIDTH="33%"
|
| 1052 |
|
|
ALIGN="right"
|
| 1053 |
|
|
VALIGN="top"
|
| 1054 |
|
|
>CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board</TD
|
| 1055 |
|
|
></TR
|
| 1056 |
|
|
></TABLE
|
| 1057 |
|
|
></DIV
|
| 1058 |
|
|
></BODY
|
| 1059 |
|
|
></HTML
|
| 1060 |
|
|
>
|
