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<HTML
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><HEAD
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>SMP Support</TITLE
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"><LINK
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REL="HOME"
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TITLE="eCos Reference Manual"
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HREF="ecos-ref.html"><LINK
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REL="UP"
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TITLE="The eCos Kernel"
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HREF="kernel.html"><LINK
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REL="PREVIOUS"
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TITLE="Kernel Overview"
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HREF="kernel-overview.html"><LINK
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TITLE="Thread creation"
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>eCos Reference Manual</TH
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WIDTH="100%"></DIV
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><H1
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><A
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NAME="KERNEL-SMP">SMP Support</H1
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><DIV
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CLASS="REFNAMEDIV"
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><A
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NAME="AEN206"
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></A
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><H2
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>Name</H2
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>SMP -- Support Symmetric Multiprocessing Systems</DIV
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><DIV
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CLASS="REFSECT1"
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><A
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NAME="KERNEL-SMP-DESCRIPTION"
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></A
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><H2
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>Description</H2
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><P
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>eCos contains support for limited Symmetric Multi-Processing (SMP).
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This is only available on selected architectures and platforms.
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The implementation has a number of restrictions on the kind of
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hardware supported. These are described in <A
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HREF="hal-smp-support.html"
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>the Section called <I
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>SMP Support</I
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> in Chapter 9</A
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>.
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</P
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><P
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>The following sections describe the changes that have been made to the
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eCos kernel to support SMP operation.
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</P
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></DIV
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><DIV
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CLASS="REFSECT1"
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><A
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NAME="KERNEL-SMP-STARTUP"
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></A
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><H2
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>System Startup</H2
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><P
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>The system startup sequence needs to be somewhat different on an SMP
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system, although this is largely transparent to application code. The
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main startup takes place on only one CPU, called the primary CPU. All
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other CPUs, the secondary CPUs, are either placed in suspended state
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at reset, or are captured by the HAL and put into a spin as they start
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up. The primary CPU is responsible for copying the DATA segment and
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zeroing the BSS (if required), calling HAL variant and platform
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initialization routines and invoking constructors. It then calls
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<TT
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CLASS="FUNCTION"
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>cyg_start</TT
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> to enter the application. The
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application may then create extra threads and other objects.
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</P
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><P
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>It is only when the application calls
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<TT
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CLASS="FUNCTION"
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>cyg_scheduler_start</TT
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> that the secondary CPUs are
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initialized. This routine scans the list of available secondary CPUs
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and invokes <TT
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CLASS="FUNCTION"
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>HAL_SMP_CPU_START</TT
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> to start each
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CPU. Finally it calls an internal function
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<TT
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CLASS="FUNCTION"
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>Cyg_Scheduler::start_cpu</TT
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> to enter the scheduler
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for the primary CPU.
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</P
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><P
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>Each secondary CPU starts in the HAL, where it completes any per-CPU
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initialization before calling into the kernel at
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<TT
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CLASS="FUNCTION"
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>cyg_kernel_cpu_startup</TT
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>. Here it claims the
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scheduler lock and calls
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<TT
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CLASS="FUNCTION"
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>Cyg_Scheduler::start_cpu</TT
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>.
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</P
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><P
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><TT
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CLASS="FUNCTION"
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>Cyg_Scheduler::start_cpu</TT
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> is common to both the
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primary and secondary CPUs. The first thing this code does is to
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install an interrupt object for this CPU's inter-CPU interrupt. From
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this point on the code is the same as for the single CPU case: an
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initial thread is chosen and entered.
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</P
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><P
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>From this point on the CPUs are all equal, eCos makes no further
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distinction between the primary and secondary CPUs. However, the
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hardware may still distinguish between them as far as interrupt
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delivery is concerned.
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</P
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></DIV
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><DIV
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CLASS="REFSECT1"
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><A
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NAME="KERNEL-SMP-SCHEDULING"
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></A
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><H2
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>Scheduling</H2
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><P
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>To function correctly an operating system kernel must protect its
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vital data structures, such as the run queues, from concurrent
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access. In a single CPU system the only concurrent activities to worry
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about are asynchronous interrupts. The kernel can easily guard its
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data structures against these by disabling interrupts. However, in a
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multi-CPU system, this is inadequate since it does not block access by
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other CPUs.
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</P
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><P
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>The eCos kernel protects its vital data structures using the scheduler
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lock. In single CPU systems this is a simple counter that is
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atomically incremented to acquire the lock and decremented to release
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it. If the lock is decremented to zero then the scheduler may be
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invoked to choose a different thread to run. Because interrupts may
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continue to be serviced while the scheduler lock is claimed, ISRs are
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not allowed to access kernel data structures, or call kernel routines
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that can. Instead all such operations are deferred to an associated
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DSR routine that is run during the lock release operation, when the
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data structures are in a consistent state.
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</P
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><P
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>By choosing a kernel locking mechanism that does not rely on interrupt
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manipulation to protect data structures, it is easier to convert eCos
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to SMP than would otherwise be the case. The principal change needed to
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make eCos SMP-safe is to convert the scheduler lock into a nestable
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spin lock. This is done by adding a spinlock and a CPU id to the
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original counter.
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</P
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><P
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>The algorithm for acquiring the scheduler lock is very simple. If the
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scheduler lock's CPU id matches the current CPU then it can just increment
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the counter and continue. If it does not match, the CPU must spin on
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the spinlock, after which it may increment the counter and store its
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own identity in the CPU id.
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</P
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><P
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>To release the lock, the counter is decremented. If it goes to zero
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the CPU id value must be set to NONE and the spinlock cleared.
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</P
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><P
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>To protect these sequences against interrupts, they must be performed
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with interrupts disabled. However, since these are very short code
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sequences, they will not have an adverse effect on the interrupt
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latency.
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</P
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><P
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>Beyond converting the scheduler lock, further preparing the kernel for
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SMP is a relatively minor matter. The main changes are to convert
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various scalar housekeeping variables into arrays indexed by CPU
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id. These include the current thread pointer, the need_reschedule
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flag and the timeslice counter.
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</P
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><P
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>At present only the Multi-Level Queue (MLQ) scheduler is capable of
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supporting SMP configurations. The main change made to this scheduler
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is to cope with having several threads in execution at the same
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time. Running threads are marked with the CPU that they are executing on.
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When scheduling a thread, the scheduler skips past any running threads
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until it finds a thread that is pending. While not a constant-time
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algorithm, as in the single CPU case, this is still deterministic,
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since the worst case time is bounded by the number of CPUs in the
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system.
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</P
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><P
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>A second change to the scheduler is in the code used to decide when
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the scheduler should be called to choose a new thread. The scheduler
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attempts to keep the <SPAN
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CLASS="PROPERTY"
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>n</SPAN
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> CPUs running the
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<SPAN
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CLASS="PROPERTY"
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>n</SPAN
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> highest priority threads. Since an event or
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interrupt on one CPU may require a reschedule on another CPU, there
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must be a mechanism for deciding this. The algorithm currently
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implemented is very simple. Given a thread that has just been awakened
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(or had its priority changed), the scheduler scans the CPUs, starting
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with the one it is currently running on, for a current thread that is
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of lower priority than the new one. If one is found then a reschedule
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interrupt is sent to that CPU and the scan continues, but now using
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the current thread of the rescheduled CPU as the candidate thread. In
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this way the new thread gets to run as quickly as possible, hopefully
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on the current CPU, and the remaining CPUs will pick up the remaining
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highest priority threads as a consequence of processing the reschedule
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interrupt.
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</P
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><P
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>The final change to the scheduler is in the handling of
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timeslicing. Only one CPU receives timer interrupts, although all CPUs
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must handle timeslicing. To make this work, the CPU that receives the
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timer interrupt decrements the timeslice counter for all CPUs, not
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just its own. If the counter for a CPU reaches zero, then it sends a
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timeslice interrupt to that CPU. On receiving the interrupt the
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destination CPU enters the scheduler and looks for another thread at
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the same priority to run. This is somewhat more efficient than
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distributing clock ticks to all CPUs, since the interrupt is only
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needed when a timeslice occurs.
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</P
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><P
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>All existing synchronization mechanisms work as before in an SMP
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system. Additional synchronization mechanisms have been added to
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provide explicit synchronization for SMP, in the form of
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<A
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HREF="kernel-spinlocks.html"
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>spinlocks</A
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>.
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</P
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></DIV
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><DIV
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CLASS="REFSECT1"
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><A
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| 304 |
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NAME="KERNEL-SMP-INTERRUPTS"
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></A
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| 306 |
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><H2
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| 307 |
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>SMP Interrupt Handling</H2
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| 308 |
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><P
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| 309 |
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>The main area where the SMP nature of a system requires special
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attention is in device drivers and especially interrupt handling. It
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is quite possible for the ISR, DSR and thread components of a device
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driver to execute on different CPUs. For this reason it is much more
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important that SMP-capable device drivers use the interrupt-related
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functions correctly. Typically a device driver would use the driver
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| 315 |
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API rather than call the kernel directly, but it is unlikely that
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anybody would attempt to use a multiprocessor system without the
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kernel package.
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</P
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| 319 |
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><P
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| 320 |
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>Two new functions have been added to the Kernel API
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|
to do <A
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| 322 |
|
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HREF="kernel-interrupts.html#KERNEL-INTERRUPTS-SMP"
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>interrupt
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| 324 |
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routing</A
|
| 325 |
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>: <TT
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| 326 |
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CLASS="FUNCTION"
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| 327 |
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|
>cyg_interrupt_set_cpu</TT
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| 328 |
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|
> and
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| 329 |
|
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<TT
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| 330 |
|
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CLASS="FUNCTION"
|
| 331 |
|
|
>cyg_interrupt_get_cpu</TT
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| 332 |
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>. Although not currently
|
| 333 |
|
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supported, special values for the cpu argument may be used in future
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| 334 |
|
|
to indicate that the interrupt is being routed dynamically or is
|
| 335 |
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CPU-local. Once a vector has been routed to a new CPU, all other
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| 336 |
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interrupt masking and configuration operations are relative to that
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| 337 |
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CPU, where relevant.
|
| 338 |
|
|
</P
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| 339 |
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|
><P
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| 340 |
|
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>There are more details of how interrupts should be handled in SMP
|
| 341 |
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|
systems in <A
|
| 342 |
|
|
HREF="devapi-smp-support.html"
|
| 343 |
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|
>the Section called <I
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| 344 |
|
|
>SMP Support</I
|
| 345 |
|
|
> in Chapter 18</A
|
| 346 |
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|
>.
|
| 347 |
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</P
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