OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [nano.html] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 unneback
<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
2
<!-- This material may be distributed only subject to the terms      -->
3
<!-- and conditions set forth in the Open Publication License, v1.0  -->
4
<!-- or later (the latest version is presently available at          -->
5
<!-- http://www.opencontent.org/openpub/).                           -->
6
<!-- Distribution of the work or derivative of the work in any       -->
7
<!-- standard (paper) book form is prohibited unless prior           -->
8
<!-- permission is obtained from the copyright holder.               -->
9
<HTML
10
><HEAD
11
><TITLE
12
>ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</TITLE
13
><meta name="MSSmartTagsPreventParsing" content="TRUE">
14
<META
15
NAME="GENERATOR"
16
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
17
"><LINK
18
REL="HOME"
19
TITLE="eCos Reference Manual"
20
HREF="ecos-ref.html"><LINK
21
REL="UP"
22
TITLE="Installation and Testing"
23
HREF="installation-and-testing.html"><LINK
24
REL="PREVIOUS"
25
TITLE="ARM/StrongARM(SA1110) Intel SA1110 (Assabet) "
26
HREF="assabet.html"><LINK
27
REL="NEXT"
28
TITLE="ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC"
29
HREF="ipaq.html"></HEAD
30
><BODY
31
CLASS="SECT1"
32
BGCOLOR="#FFFFFF"
33
TEXT="#000000"
34
LINK="#0000FF"
35
VLINK="#840084"
36
ALINK="#0000FF"
37
><DIV
38
CLASS="NAVHEADER"
39
><TABLE
40
SUMMARY="Header navigation table"
41
WIDTH="100%"
42
BORDER="0"
43
CELLPADDING="0"
44
CELLSPACING="0"
45
><TR
46
><TH
47
COLSPAN="3"
48
ALIGN="center"
49
>eCos Reference Manual</TH
50
></TR
51
><TR
52
><TD
53
WIDTH="10%"
54
ALIGN="left"
55
VALIGN="bottom"
56
><A
57
HREF="assabet.html"
58
ACCESSKEY="P"
59
>Prev</A
60
></TD
61
><TD
62
WIDTH="80%"
63
ALIGN="center"
64
VALIGN="bottom"
65
>Chapter 5. Installation and Testing</TD
66
><TD
67
WIDTH="10%"
68
ALIGN="right"
69
VALIGN="bottom"
70
><A
71
HREF="ipaq.html"
72
ACCESSKEY="N"
73
>Next</A
74
></TD
75
></TR
76
></TABLE
77
><HR
78
ALIGN="LEFT"
79
WIDTH="100%"></DIV
80
><DIV
81
CLASS="SECT1"
82
><H1
83
CLASS="SECT1"
84
><A
85
NAME="NANO">ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</H1
86
><DIV
87
CLASS="SECT2"
88
><H2
89
CLASS="SECT2"
90
><A
91
NAME="AEN5802">Overview</H2
92
><P
93
>RedBoot supports a serial port and the built in ethernet port
94
for communication and downloads. The default serial port settings are 38400,8,N,1.
95
RedBoot runs from and supports flash management for the system flash
96
region.</P
97
><P
98
>The following RedBoot configurations are supported:
99
 
100
      <DIV
101
CLASS="INFORMALTABLE"
102
><A
103
NAME="AEN5818"><P
104
></P
105
><TABLE
106
BORDER="1"
107
CLASS="CALSTABLE"
108
><THEAD
109
><TR
110
><TH
111
ALIGN="LEFT"
112
VALIGN="TOP"
113
>Configuration</TH
114
><TH
115
ALIGN="LEFT"
116
VALIGN="TOP"
117
>Mode</TH
118
><TH
119
ALIGN="LEFT"
120
VALIGN="TOP"
121
>Description</TH
122
><TH
123
ALIGN="LEFT"
124
VALIGN="TOP"
125
>File</TH
126
></TR
127
></THEAD
128
><TBODY
129
><TR
130
><TD
131
ALIGN="LEFT"
132
VALIGN="TOP"
133
>POST</TD
134
><TD
135
ALIGN="LEFT"
136
VALIGN="TOP"
137
>[ROM]</TD
138
><TD
139
ALIGN="LEFT"
140
VALIGN="TOP"
141
>RedBoot running from the first free flash block
142
              at 0x40000.</TD
143
><TD
144
ALIGN="LEFT"
145
VALIGN="TOP"
146
>redboot_ROM.ecm</TD
147
></TR
148
><TR
149
><TD
150
ALIGN="LEFT"
151
VALIGN="TOP"
152
>RAM</TD
153
><TD
154
ALIGN="LEFT"
155
VALIGN="TOP"
156
>[RAM]</TD
157
><TD
158
ALIGN="LEFT"
159
VALIGN="TOP"
160
>RedBoot running from RAM with RedBoot in the
161
              flash boot sector.</TD
162
><TD
163
ALIGN="LEFT"
164
VALIGN="TOP"
165
>redboot_RAM.ecm</TD
166
></TR
167
></TBODY
168
></TABLE
169
><P
170
></P
171
></DIV
172
></P
173
></DIV
174
><DIV
175
CLASS="SECT2"
176
><H2
177
CLASS="SECT2"
178
><A
179
NAME="AEN5837">Initial Installation</H2
180
><P
181
>Unlike other targets, the nanoEngine comes equipped with boot firmware
182
which you cannot modify.  See chapter 5, "nanoEngine Firmware" of the <I
183
CLASS="CITETITLE"
184
>nanoEngine Hardware Reference Manual</I
185
> (we refer to "July 17, 2000
186
Rev 0.6") from Bright Star Engineering. </P
187
><P
188
>Because of this, eCos, and therefore Redboot, only supports a
189
special configuration of the ROM mode, starting at offset 0x40000 in
190
the flash.</P
191
><P
192
>Briefly, the POST-configuration RedBoot image lives in flash following the
193
BSE firmware. The BSE firmware is configured, using its standard <B
194
CLASS="COMMAND"
195
>bootcmd</B
196
> command, to run RedBoot at startup.</P
197
></DIV
198
><DIV
199
CLASS="SECT2"
200
><H2
201
CLASS="SECT2"
202
><A
203
NAME="AEN5844">Download Instructions</H2
204
><P
205
>You can perform the initial load of the POST-configuration RedBoot image into
206
flash using the BSE firmware's <B
207
CLASS="COMMAND"
208
>load</B
209
> command.
210
This will load a binary file, using TFTP, and program it into flash in one
211
operation. Because no memory management is used in the BSE firmware, flash
212
is mapped from address zero upwards, so the address for the RedBoot POST image
213
is 0x40000.  You must use the binary version of RedBoot for this,
214
<TT
215
CLASS="FILENAME"
216
>redboot-post.bin</TT
217
>.</P
218
><P
219
>This assumes you have set up the other BSE firmware config
220
parameters such that it can communicate over your network to your TFTP
221
server.
222
<TABLE
223
BORDER="5"
224
BGCOLOR="#E0E0F0"
225
WIDTH="70%"
226
><TR
227
><TD
228
><PRE
229
CLASS="SCREEN"
230
>&#62;<TT
231
CLASS="USERINPUT"
232
><B
233
>load redboot-post.bin 40000</B
234
></TT
235
>
236
loading ... erasing blk at 00040000
237
erasing blk at 00050000
238
94168 bytes loaded cksum 00008579
239
done
240
&#62;
241
&#62; <TT
242
CLASS="USERINPUT"
243
><B
244
>set bootcmd "go 40000"</B
245
></TT
246
>
247
&#62; <TT
248
CLASS="USERINPUT"
249
><B
250
>get</B
251
></TT
252
>
253
myip = 10.16.19.198
254
netmask = 255.255.255.0
255
eth = 0
256
gateway = 10.16.19.66
257
serverip = 10.16.19.66
258
bootcmd = go 40000
259
&#62;</PRE
260
></TD
261
></TR
262
></TABLE
263
>
264
 
265
<DIV
266
CLASS="NOTE"
267
><BLOCKQUOTE
268
CLASS="NOTE"
269
><P
270
><B
271
>NOTE: </B
272
>the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead
273
at 38400 Baud. You must select the right baud rate in your terminal program
274
to be able to set up the BSE firmware.</P
275
></BLOCKQUOTE
276
></DIV
277
>
278
 
279
After a reset, the BSE firmware will print
280
 
281
<TABLE
282
BORDER="5"
283
BGCOLOR="#E0E0F0"
284
WIDTH="70%"
285
><TR
286
><TD
287
><PRE
288
CLASS="SCREEN"
289
>Boot: BSE 2000 Sep 12 2000 14:00:30
290
autoboot: "go 40000" [hit ESC to abort]</PRE
291
></TD
292
></TR
293
></TABLE
294
>
295
 
296
and then RedBoot starts, switching to 38400 Baud.</P
297
><P
298
>Once you have installed a bootable RedBoot in the system in this
299
manner, we advise re-installing using the generic method described in
300
<A
301
HREF="updating-redboot.html"
302
>Chapter 4</A
303
> in order that the Flash Image System
304
contains an appropriate description of the flash entries.</P
305
></DIV
306
><DIV
307
CLASS="SECT2"
308
><H2
309
CLASS="SECT2"
310
><A
311
NAME="AEN5860">Cohabiting with POST in Flash</H2
312
><P
313
>The configuration file named <TT
314
CLASS="FILENAME"
315
>redboot_POST.ecm</TT
316
>
317
configures RedBoot to build for execution at address 0x50040000 (or, during
318
bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable
319
firmware to live in the lower addresses of the flash and to run before RedBoot
320
gets control. The assumption is that RedBoot will be entered at its base address
321
in physical memory, that is 0x00040000.</P
322
><P
323
>Alternatively, for testing, you can call it in an already running system
324
by using <TT
325
CLASS="USERINPUT"
326
><B
327
>go 0x50040040</B
328
></TT
329
> at another RedBoot prompt, or
330
a branch to that address. The address is where the reset vector
331
points. It is reported by RedBoot's <B
332
CLASS="COMMAND"
333
>load</B
334
> command
335
and listed
336
by the <B
337
CLASS="COMMAND"
338
>fis list</B
339
> command, amongst other
340
places.</P
341
><P
342
>Using the POST configuration enables a normal config option which causes
343
linking and initialization against memory layout files called "...post..."
344
rather than "...rom..." or "...ram..." in the <TT
345
CLASS="FILENAME"
346
>include/pkgconf</TT
347
> directory. Specifically:<P
348
CLASS="LITERALLAYOUT"
349
><TT
350
CLASS="FILENAME"
351
>include/pkgconf/mlt_arm_sa11x0_nano_post.h</TT
352
><br>
353
<TT
354
CLASS="FILENAME"
355
>include/pkgconf/mlt_arm_sa11x0_nano_post.ldi</TT
356
><br>
357
<TT
358
CLASS="FILENAME"
359
>include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</TT
360
></P
361
>
362
 
363
It is these you should edit if you wish to move the execution address
364
from 0x50040000 in the POST configuration.  Startup mode naturally
365
remains ROM in this configuration.</P
366
><P
367
>Because the nanoEngine contains immutable boot firmware at the start
368
of flash, RedBoot for this target is configured to reserve that area in the
369
Flash Image System, and to create by default an entry for the POST
370
mode RedBoot.
371
<TABLE
372
BORDER="5"
373
BGCOLOR="#E0E0F0"
374
WIDTH="70%"
375
><TR
376
><TD
377
><PRE
378
CLASS="SCREEN"
379
>RedBoot&#62; <TT
380
CLASS="USERINPUT"
381
><B
382
>fis list</B
383
></TT
384
>
385
Name              FLASH addr  Mem addr    Length      Entry point
386
(reserved)        0x50000000  0x50000000  0x00040000  0x00000000
387
RedBoot[post]     0x50040000  0x00100000  0x00020000  0x50040040
388
RedBoot config    0x503E0000  0x503E0000  0x00010000  0x00000000
389
FIS directory     0x503F0000  0x503F0000  0x00010000  0x00000000
390
RedBoot&#62;</PRE
391
></TD
392
></TR
393
></TABLE
394
>
395
The entry "(reserved)" ensures that the FIS cannot attempt
396
to overwrite the BSE firmware, thus ensuring that the board remains bootable
397
and recoverable even after installing a broken RedBoot image.</P
398
></DIV
399
><DIV
400
CLASS="SECT2"
401
><H2
402
CLASS="SECT2"
403
><A
404
NAME="AEN5877">Special RedBoot Commands</H2
405
><P
406
>The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers
407
installed, but these have no associated serial EEPROM in which to record their
408
Ethernet Station Address (ESA, or MAC address). The BSE firmware records an
409
ESA for the device it uses, but this information is not available to RedBoot;
410
we cannot share it.</P
411
><P
412
>To keep the ESAs for the two ethernet interfaces, two new items of RedBoot
413
configuration data are introduced.  You can list them with the RedBoot command <B
414
CLASS="COMMAND"
415
>fconfig -l</B
416
> thus:
417
<TABLE
418
BORDER="5"
419
BGCOLOR="#E0E0F0"
420
WIDTH="70%"
421
><TR
422
><TD
423
><PRE
424
CLASS="SCREEN"
425
>RedBoot&#62; <TT
426
CLASS="USERINPUT"
427
><B
428
>fconfig -l</B
429
></TT
430
>
431
Run script at boot: false
432
Use BOOTP for network configuration: false
433
Local IP address: 10.16.19.91
434
Default server IP address: 10.16.19.66
435
Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99
436
Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A
437
GDB connection port: 9000
438
Network debug at boot time: false
439
RedBoot&#62;</PRE
440
></TD
441
></TR
442
></TABLE
443
>
444
 
445
You should set them before running RedBoot or eCos applications with
446
the board connected to a network. The <B
447
CLASS="COMMAND"
448
>fconfig </B
449
>
450
command can be used as for any configuration data item; the entire ESA
451
is entered in one line.</P
452
></DIV
453
><DIV
454
CLASS="SECT2"
455
><H2
456
CLASS="SECT2"
457
><A
458
NAME="AEN5885">Memory Maps</H2
459
><P
460
>The first level page table is located at physical address 0xc0004000.
461
 No second level tables are used.   <DIV
462
CLASS="NOTE"
463
><BLOCKQUOTE
464
CLASS="NOTE"
465
><P
466
><B
467
>NOTE: </B
468
>The virtual memory maps in this section use a C and B column to indicate
469
whether or not the region is cached (C) or buffered (B).</P
470
></BLOCKQUOTE
471
></DIV
472
><TABLE
473
BORDER="5"
474
BGCOLOR="#E0E0F0"
475
WIDTH="70%"
476
><TR
477
><TD
478
><PRE
479
CLASS="PROGRAMLISTING"
480
>Physical Address Range     Description
481
-----------------------    ----------------------------------
482
0x00000000 - 0x003fffff    4Mb FLASH (nCS0)
483
0x18000000 - 0x18ffffff    Internal PCI bus - 2 x i82559 ethernet
484
0x40000000 - 0x4fffffff    External IO or PCI bus
485
0x80000000 - 0xbfffffff    SA-1110 Internal Registers
486
0xc0000000 - 0xc7ffffff    DRAM Bank 0 - 32Mb SDRAM
487
0xc8000000 - 0xcfffffff    DRAM Bank 1 - empty
488
0xe0000000 - 0xe7ffffff    Cache Clean
489
 
490
Virtual Address Range    C B  Description
491
-----------------------  - -  ----------------------------------
492
0x00000000 - 0x001fffff  Y Y  DRAM - 8Mb to 32Mb
493
0x18000000 - 0x180fffff  N N  Internal PCI bus - 2 x i82559 ethernet
494
0x40000000 - 0x4fffffff  N N  External IO or PCI bus
495
0x50000000 - 0x51ffffff  Y Y  Up to 32Mb FLASH (nCS0)
496
0x80000000 - 0xbfffffff  N N  SA-1110 Internal Registers
497
0xc0000000 - 0xc0ffffff  N Y  DRAM Bank 0: 8 or 16Mb
498
0xc8000000 - 0xc8ffffff  N Y  DRAM Bank 1: 8 or 16Mb or absent
499
0xe0000000 - 0xe7ffffff  Y Y  Cache Clean</PRE
500
></TD
501
></TR
502
></TABLE
503
></P
504
><P
505
>The ethernet devices use a "PCI window" to communicate with the CPU.
506
This is 1Mb of SDRAM which is shared with the ethernet devices that are on
507
the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI
508
accesses see correct data in the correct order. By default it is configured
509
to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be
510
modified, and indeed must be, if less than 32Mb of SDRAM is installed, via
511
the memory layout tool, or by moving the section <TT
512
CLASS="COMPUTEROUTPUT"
513
>__pci_window</TT
514
> referred to by symbols <TT
515
CLASS="COMPUTEROUTPUT"
516
>CYGMEM_SECTION_pci_window*</TT
517
> in the linker script.   </P
518
><P
519
>Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM
520
bank 0, the code can cope with any of these combinations also; "2 x " in this
521
context means one device in each DRAM Bank.     <P
522
CLASS="LITERALLAYOUT"
523
>1&nbsp;x&nbsp;8Mb&nbsp;=&nbsp;8Mb&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;2&nbsp;x&nbsp;8Mb&nbsp;=&nbsp;16Mb<br>
524
1&nbsp;x&nbsp;16Mb&nbsp;=&nbsp;16Mb&nbsp;&nbsp;&nbsp;2&nbsp;x&nbsp;16Mb&nbsp;=&nbsp;32Mb</P
525
>All are programmed the same
526
in the memory controller.   </P
527
><P
528
>Startup code detects which is fitted and programs the memory map accordingly.
529
If the device(s) is 8Mb, then there are gaps in the physical memory map, because
530
a high order address bit is not connected. The gaps are the higher 2Mb out
531
of every 4Mb.</P
532
><P
533
> The SA11x0 OS timer is used as a polled timer to provide timeout
534
support within RedBoot.</P
535
></DIV
536
><DIV
537
CLASS="SECT2"
538
><H2
539
CLASS="SECT2"
540
><A
541
NAME="AEN5899">Nano Platform Port</H2
542
><P
543
>The nano is in the set of SA11X0-based platforms. It uses the arm architectural
544
HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components
545
        <P
546
CLASS="LITERALLAYOUT"
547
>CYGPKG_HAL_ARM&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/arch/<br>
548
CYGPKG_HAL_ARM_SA11X0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/sa11x0/var<br>
549
CYGPKG_HAL_ARM_SA11X0_NANO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;hal/arm/sa11x0/nano</P
550
> respectively.
551
  </P
552
><P
553
>The target name is "nano" which includes all these, plus the ethernet
554
driver packages, flash driver, and so on.</P
555
></DIV
556
><DIV
557
CLASS="SECT2"
558
><H2
559
CLASS="SECT2"
560
><A
561
NAME="AEN5904">Ethernet Driver</H2
562
><P
563
>The ethernet driver is in two parts:   </P
564
><P
565
>A generic ether driver for Intel i8255x series devices, specifically
566
the i82559, is <TT
567
CLASS="COMPUTEROUTPUT"
568
>devs/eth/intel/i82559</TT
569
>.  Its
570
package name is <TT
571
CLASS="COMPUTEROUTPUT"
572
>CYGPKG_DEVS_ETH_INTEL_I82559</TT
573
>.
574
  </P
575
><P
576
>The platform-specific ether driver is <TT
577
CLASS="COMPUTEROUTPUT"
578
>devs/eth/arm/nano</TT
579
>.  Its package is <TT
580
CLASS="COMPUTEROUTPUT"
581
>CYGPKG_DEVS_ETH_ARM_NANO</TT
582
>.  This tells the generic driver the address in IO memory
583
of the chip, for example, and other configuration details. This driver picks
584
up the ESA from RedBoot's configuration data - unless configured to use a
585
static ESA in the usual manner. </P
586
></DIV
587
><DIV
588
CLASS="SECT2"
589
><H2
590
CLASS="SECT2"
591
><A
592
NAME="AEN5913">Rebuilding RedBoot</H2
593
><P
594
>These shell variables provide the platform-specific information
595
needed for building RedBoot according to the procedure described in
596
<A
597
HREF="rebuilding-redboot.html"
598
>Chapter 3</A
599
>:
600
<TABLE
601
BORDER="5"
602
BGCOLOR="#E0E0F0"
603
WIDTH="70%"
604
><TR
605
><TD
606
><PRE
607
CLASS="PROGRAMLISTING"
608
>export TARGET=nano
609
export ARCH_DIR=arm
610
export PLATFORM_DIR=sa11x0/nano</PRE
611
></TD
612
></TR
613
></TABLE
614
></P
615
><P
616
>The names of configuration files are listed above with the
617
description of the associated modes.</P
618
></DIV
619
></DIV
620
><DIV
621
CLASS="NAVFOOTER"
622
><HR
623
ALIGN="LEFT"
624
WIDTH="100%"><TABLE
625
SUMMARY="Footer navigation table"
626
WIDTH="100%"
627
BORDER="0"
628
CELLPADDING="0"
629
CELLSPACING="0"
630
><TR
631
><TD
632
WIDTH="33%"
633
ALIGN="left"
634
VALIGN="top"
635
><A
636
HREF="assabet.html"
637
ACCESSKEY="P"
638
>Prev</A
639
></TD
640
><TD
641
WIDTH="34%"
642
ALIGN="center"
643
VALIGN="top"
644
><A
645
HREF="ecos-ref.html"
646
ACCESSKEY="H"
647
>Home</A
648
></TD
649
><TD
650
WIDTH="33%"
651
ALIGN="right"
652
VALIGN="top"
653
><A
654
HREF="ipaq.html"
655
ACCESSKEY="N"
656
>Next</A
657
></TD
658
></TR
659
><TR
660
><TD
661
WIDTH="33%"
662
ALIGN="left"
663
VALIGN="top"
664
>ARM/StrongARM(SA1110) Intel SA1110 (Assabet)</TD
665
><TD
666
WIDTH="34%"
667
ALIGN="center"
668
VALIGN="top"
669
><A
670
HREF="installation-and-testing.html"
671
ACCESSKEY="U"
672
>Up</A
673
></TD
674
><TD
675
WIDTH="33%"
676
ALIGN="right"
677
VALIGN="top"
678
>ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC</TD
679
></TR
680
></TABLE
681
></DIV
682
></BODY
683
></HTML
684
>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.