OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [ocelot.html] - Blame information for rev 510

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 unneback
<!-- Copyright (C) 2003 Red Hat, Inc.                                -->
2
<!-- This material may be distributed only subject to the terms      -->
3
<!-- and conditions set forth in the Open Publication License, v1.0  -->
4
<!-- or later (the latest version is presently available at          -->
5
<!-- http://www.opencontent.org/openpub/).                           -->
6
<!-- Distribution of the work or derivative of the work in any       -->
7
<!-- standard (paper) book form is prohibited unless prior           -->
8
<!-- permission is obtained from the copyright holder.               -->
9
<HTML
10
><HEAD
11
><TITLE
12
>MIPS/RM7000 PMC-Sierra Ocelot</TITLE
13
><meta name="MSSmartTagsPreventParsing" content="TRUE">
14
<META
15
NAME="GENERATOR"
16
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
17
"><LINK
18
REL="HOME"
19
TITLE="eCos Reference Manual"
20
HREF="ecos-ref.html"><LINK
21
REL="UP"
22
TITLE="Installation and Testing"
23
HREF="installation-and-testing.html"><LINK
24
REL="PREVIOUS"
25
TITLE="MIPS/MIPS32(CoreLV 4Kc)+MIPS64(CoreLV 5Kc) Malta Board "
26
HREF="malta.html"><LINK
27
REL="NEXT"
28
TITLE="MIPS/VR4375 NEC DDB-VRC4375"
29
HREF="vrc4375.html"></HEAD
30
><BODY
31
CLASS="SECT1"
32
BGCOLOR="#FFFFFF"
33
TEXT="#000000"
34
LINK="#0000FF"
35
VLINK="#840084"
36
ALINK="#0000FF"
37
><DIV
38
CLASS="NAVHEADER"
39
><TABLE
40
SUMMARY="Header navigation table"
41
WIDTH="100%"
42
BORDER="0"
43
CELLPADDING="0"
44
CELLSPACING="0"
45
><TR
46
><TH
47
COLSPAN="3"
48
ALIGN="center"
49
>eCos Reference Manual</TH
50
></TR
51
><TR
52
><TD
53
WIDTH="10%"
54
ALIGN="left"
55
VALIGN="bottom"
56
><A
57
HREF="malta.html"
58
ACCESSKEY="P"
59
>Prev</A
60
></TD
61
><TD
62
WIDTH="80%"
63
ALIGN="center"
64
VALIGN="bottom"
65
>Chapter 5. Installation and Testing</TD
66
><TD
67
WIDTH="10%"
68
ALIGN="right"
69
VALIGN="bottom"
70
><A
71
HREF="vrc4375.html"
72
ACCESSKEY="N"
73
>Next</A
74
></TD
75
></TR
76
></TABLE
77
><HR
78
ALIGN="LEFT"
79
WIDTH="100%"></DIV
80
><DIV
81
CLASS="SECT1"
82
><H1
83
CLASS="SECT1"
84
><A
85
NAME="OCELOT">MIPS/RM7000 PMC-Sierra Ocelot</H1
86
><DIV
87
CLASS="SECT2"
88
><H2
89
CLASS="SECT2"
90
><A
91
NAME="AEN6944">Overview</H2
92
><P
93
>RedBoot
94
uses the front facing serial port. The default serial port settings are 38400,8,N,1.
95
RedBoot also supports ethernet. Management of onboard flash is also supported.</P
96
><P
97
>The following RedBoot configurations are supported:
98
 
99
      <DIV
100
CLASS="INFORMALTABLE"
101
><A
102
NAME="AEN6954"><P
103
></P
104
><TABLE
105
BORDER="1"
106
CLASS="CALSTABLE"
107
><THEAD
108
><TR
109
><TH
110
ALIGN="LEFT"
111
VALIGN="TOP"
112
>Configuration</TH
113
><TH
114
ALIGN="LEFT"
115
VALIGN="TOP"
116
>Mode</TH
117
><TH
118
ALIGN="LEFT"
119
VALIGN="TOP"
120
>Description</TH
121
><TH
122
ALIGN="LEFT"
123
VALIGN="TOP"
124
>File</TH
125
></TR
126
></THEAD
127
><TBODY
128
><TR
129
><TD
130
ALIGN="LEFT"
131
VALIGN="TOP"
132
>ROM</TD
133
><TD
134
ALIGN="LEFT"
135
VALIGN="TOP"
136
>[ROM]</TD
137
><TD
138
ALIGN="LEFT"
139
VALIGN="TOP"
140
>RedBoot running from the board's flash boot
141
              sector.</TD
142
><TD
143
ALIGN="LEFT"
144
VALIGN="TOP"
145
>redboot_ROM.ecm</TD
146
></TR
147
><TR
148
><TD
149
ALIGN="LEFT"
150
VALIGN="TOP"
151
>RAM</TD
152
><TD
153
ALIGN="LEFT"
154
VALIGN="TOP"
155
>[RAM]</TD
156
><TD
157
ALIGN="LEFT"
158
VALIGN="TOP"
159
>RedBoot running from RAM with RedBoot in the
160
              flash boot sector.</TD
161
><TD
162
ALIGN="LEFT"
163
VALIGN="TOP"
164
>redboot_RAM.ecm</TD
165
></TR
166
></TBODY
167
></TABLE
168
><P
169
></P
170
></DIV
171
></P
172
></DIV
173
><DIV
174
CLASS="SECT2"
175
><H2
176
CLASS="SECT2"
177
><A
178
NAME="AEN6973">Additional commands</H2
179
><P
180
>The <B
181
CLASS="COMMAND"
182
>exec</B
183
> command which allows the
184
loading and execution of Linux kernels, is supported for this architecture
185
 (see <A
186
HREF="executing-programs.html"
187
>the Section called <I
188
>Executing Programs from RedBoot</I
189
> in Chapter 2</A
190
>). The
191
<B
192
CLASS="COMMAND"
193
>exec</B
194
> parameters used for MIPS boards are:</P
195
><P
196
></P
197
><DIV
198
CLASS="VARIABLELIST"
199
><DL
200
><DT
201
>-b <TT
202
CLASS="REPLACEABLE"
203
><I
204
>&lt;addr&#62;</I
205
></TT
206
></DT
207
><DD
208
><P
209
>Location to store command line and environment passed to kernel</P
210
></DD
211
><DT
212
>-w <TT
213
CLASS="REPLACEABLE"
214
><I
215
>&lt;time&#62;</I
216
></TT
217
></DT
218
><DD
219
><P
220
>Wait time in seconds before starting kernel</P
221
></DD
222
><DT
223
>-c <TT
224
CLASS="REPLACEABLE"
225
><I
226
>"params"</I
227
></TT
228
></DT
229
><DD
230
><P
231
>Parameters passed to kernel</P
232
></DD
233
><DT
234
><TT
235
CLASS="REPLACEABLE"
236
><I
237
>&lt;addr&#62;</I
238
></TT
239
></DT
240
><DD
241
><P
242
>Kernel entry point, defaulting to the entry point of the last image
243
loaded</P
244
></DD
245
></DL
246
></DIV
247
><P
248
>Linux kernels on MIPS platforms expect the entry point to be called with arguments
249
in the registers equivalent to a C call with prototype:
250
<TABLE
251
BORDER="5"
252
BGCOLOR="#E0E0F0"
253
WIDTH="70%"
254
><TR
255
><TD
256
><PRE
257
CLASS="PROGRAMLISTING"
258
>void Linux(int argc, char **argv, char **envp);</PRE
259
></TD
260
></TR
261
></TABLE
262
></P
263
><P
264
>RedBoot will place the appropriate data at the offset specified by the
265
<TT
266
CLASS="PARAMETER"
267
><I
268
>-b</I
269
></TT
270
> parameter, or by default at address 0x80080000, and will set the
271
arguments accordingly when calling into the kernel.</P
272
><P
273
>The default entry point, if no image with explicit entry point has been loaded and
274
none is specified, is 0x80000750.</P
275
></DIV
276
><DIV
277
CLASS="SECT2"
278
><H2
279
CLASS="SECT2"
280
><A
281
NAME="AEN7005">Memory Maps</H2
282
><P
283
>RedBoot sets up the following memory map on the Ocelot board. </P
284
><P
285
>Note that these addresses are accessed through kseg0/1 and thus translate
286
to the actual address range 0x80000000-0xbfffffff, depending on the need for
287
caching/non-caching access to the bus.<DIV
288
CLASS="NOTE"
289
><BLOCKQUOTE
290
CLASS="NOTE"
291
><P
292
><B
293
>NOTE: </B
294
>The virtual memory maps in this section use a C and B column to indicate
295
whether or not the region is cached (C) or buffered (B).</P
296
></BLOCKQUOTE
297
></DIV
298
><TABLE
299
BORDER="5"
300
BGCOLOR="#E0E0F0"
301
WIDTH="70%"
302
><TR
303
><TD
304
><PRE
305
CLASS="PROGRAMLISTING"
306
>Physical Address Range Description
307
----------------------- -----------
308
0x00000000 - 0x0fffffff SDRAM
309
0x10000000 - 0x10ffffff PCI I/O space
310
0x12000000 - 0x13ffffff PCI Memory space
311
0x14000000 - 0x1400ffff Galileo system controller
312
0x1c000000 - 0x1c0000ff PLD (board logic)
313
0x1fc00000 - 0x1fc7ffff flash</PRE
314
></TD
315
></TR
316
></TABLE
317
></P
318
></DIV
319
><DIV
320
CLASS="SECT2"
321
><H2
322
CLASS="SECT2"
323
><A
324
NAME="AEN7013">Rebuilding RedBoot</H2
325
><P
326
>These shell variables provide the platform-specific information
327
needed for building RedBoot according to the procedure described in
328
<A
329
HREF="rebuilding-redboot.html"
330
>Chapter 3</A
331
>:
332
<TABLE
333
BORDER="5"
334
BGCOLOR="#E0E0F0"
335
WIDTH="70%"
336
><TR
337
><TD
338
><PRE
339
CLASS="PROGRAMLISTING"
340
>export TARGET=ocelot
341
export ARCH_DIR=mips
342
export PLATFORM_DIR=rm7000/ocelot</PRE
343
></TD
344
></TR
345
></TABLE
346
></P
347
><P
348
>The names of configuration files are listed above with the
349
description of the associated modes.</P
350
></DIV
351
></DIV
352
><DIV
353
CLASS="NAVFOOTER"
354
><HR
355
ALIGN="LEFT"
356
WIDTH="100%"><TABLE
357
SUMMARY="Footer navigation table"
358
WIDTH="100%"
359
BORDER="0"
360
CELLPADDING="0"
361
CELLSPACING="0"
362
><TR
363
><TD
364
WIDTH="33%"
365
ALIGN="left"
366
VALIGN="top"
367
><A
368
HREF="malta.html"
369
ACCESSKEY="P"
370
>Prev</A
371
></TD
372
><TD
373
WIDTH="34%"
374
ALIGN="center"
375
VALIGN="top"
376
><A
377
HREF="ecos-ref.html"
378
ACCESSKEY="H"
379
>Home</A
380
></TD
381
><TD
382
WIDTH="33%"
383
ALIGN="right"
384
VALIGN="top"
385
><A
386
HREF="vrc4375.html"
387
ACCESSKEY="N"
388
>Next</A
389
></TD
390
></TR
391
><TR
392
><TD
393
WIDTH="33%"
394
ALIGN="left"
395
VALIGN="top"
396
>MIPS/MIPS32(CoreLV 4Kc)+MIPS64(CoreLV 5Kc) Malta Board</TD
397
><TD
398
WIDTH="34%"
399
ALIGN="center"
400
VALIGN="top"
401
><A
402
HREF="installation-and-testing.html"
403
ACCESSKEY="U"
404
>Up</A
405
></TD
406
><TD
407
WIDTH="33%"
408
ALIGN="right"
409
VALIGN="top"
410
>MIPS/VR4375 NEC DDB-VRC4375</TD
411
></TR
412
></TABLE
413
></DIV
414
></BODY
415
></HTML
416
>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.