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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [cygmon/] [v2_0/] [misc/] [bsp/] [arm/] [gdb-cpu.c] - Blame information for rev 174

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1 27 unneback 
//==========================================================================
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//
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//      gdb-cpu.c
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//
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//      CPU specific support for GDB stub.
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):
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// Contributors: gthomas
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// Date:         1999-10-20
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// Purpose:      CPU specific support for GDB stub.
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// Description:  ARM is a Registered Trademark of Advanced RISC Machines
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//               Limited.
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//               Other Brands and Trademarks are the property of their
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//               respective owners.
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//
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//####DESCRIPTIONEND####
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//
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//=========================================================================
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#include <bsp/cpu.h>
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#include <bsp/bsp.h>
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#include "insn.h"
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#include "gdb.h"
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/*
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 * Return byte offset within the saved register area of the
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 * given register.
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 */
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int
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bsp_regbyte(int regno)
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{
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    switch(regno)
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    {
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    case REG_R0:   return (int)&(((ex_regs_t*)0)->_r0);   break;
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    case REG_R1:   return (int)&(((ex_regs_t*)0)->_r1);   break;
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    case REG_R2:   return (int)&(((ex_regs_t*)0)->_r2);   break;
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    case REG_R3:   return (int)&(((ex_regs_t*)0)->_r3);   break;
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    case REG_R4:   return (int)&(((ex_regs_t*)0)->_r4);   break;
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    case REG_R5:   return (int)&(((ex_regs_t*)0)->_r5);   break;
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    case REG_R6:   return (int)&(((ex_regs_t*)0)->_r6);   break;
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    case REG_R7:   return (int)&(((ex_regs_t*)0)->_r7);   break;
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    case REG_R8:   return (int)&(((ex_regs_t*)0)->_r8);   break;
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    case REG_R9:   return (int)&(((ex_regs_t*)0)->_r9);   break;
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    case REG_R10:  return (int)&(((ex_regs_t*)0)->_r10);  break;
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    case REG_R11:  return (int)&(((ex_regs_t*)0)->_r11);  break;
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    case REG_R12:  return (int)&(((ex_regs_t*)0)->_r12);  break;
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    case REG_SP:   return (int)&(((ex_regs_t*)0)->_sp);   break;
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    case REG_LR:   return (int)&(((ex_regs_t*)0)->_lr);   break;
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    case REG_PC:   return (int)&(((ex_regs_t*)0)->_pc);   break;
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#ifndef __ECOS__
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    case REG_F0:   return (int)&(((ex_regs_t*)0)->_f0);   break;
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    case REG_F1:   return (int)&(((ex_regs_t*)0)->_f1);   break;
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    case REG_F2:   return (int)&(((ex_regs_t*)0)->_f2);   break;
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    case REG_F3:   return (int)&(((ex_regs_t*)0)->_f3);   break;
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    case REG_F4:   return (int)&(((ex_regs_t*)0)->_f4);   break;
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    case REG_F5:   return (int)&(((ex_regs_t*)0)->_f5);   break;
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    case REG_F6:   return (int)&(((ex_regs_t*)0)->_f6);   break;
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    case REG_F7:   return (int)&(((ex_regs_t*)0)->_f7);   break;
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    case REG_FPS:  return (int)&(((ex_regs_t*)0)->_fps);  break;
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#endif
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    case REG_CPSR: return (int)&(((ex_regs_t*)0)->_cpsr);  break;
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    case REG_SPSVC: return (int)&(((ex_regs_t*)0)->_spsvc);  break;
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    }
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    return 0;
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}
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/*
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 * Return size in bytes of given register.
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 */
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int
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bsp_regsize(int regno)
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{
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    switch(regno)
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    {
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    case REG_R0:   return (sizeof (((ex_regs_t*)0)->_r0));   break;
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    case REG_R1:   return (sizeof (((ex_regs_t*)0)->_r1));   break;
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    case REG_R2:   return (sizeof (((ex_regs_t*)0)->_r2));   break;
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    case REG_R3:   return (sizeof (((ex_regs_t*)0)->_r3));   break;
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    case REG_R4:   return (sizeof (((ex_regs_t*)0)->_r4));   break;
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    case REG_R5:   return (sizeof (((ex_regs_t*)0)->_r5));   break;
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    case REG_R6:   return (sizeof (((ex_regs_t*)0)->_r6));   break;
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    case REG_R7:   return (sizeof (((ex_regs_t*)0)->_r7));   break;
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    case REG_R8:   return (sizeof (((ex_regs_t*)0)->_r8));   break;
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    case REG_R9:   return (sizeof (((ex_regs_t*)0)->_r9));   break;
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    case REG_R10:  return (sizeof (((ex_regs_t*)0)->_r10));  break;
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    case REG_R11:  return (sizeof (((ex_regs_t*)0)->_r11));  break;
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    case REG_R12:  return (sizeof (((ex_regs_t*)0)->_r12));  break;
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    case REG_SP:   return (sizeof (((ex_regs_t*)0)->_sp));   break;
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    case REG_LR:   return (sizeof (((ex_regs_t*)0)->_lr));   break;
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    case REG_PC:   return (sizeof (((ex_regs_t*)0)->_pc));   break;
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#ifndef __ECOS__
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    case REG_F0:   return (sizeof (((ex_regs_t*)0)->_f0));   break;
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    case REG_F1:   return (sizeof (((ex_regs_t*)0)->_f1));   break;
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    case REG_F2:   return (sizeof (((ex_regs_t*)0)->_f2));   break;
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    case REG_F3:   return (sizeof (((ex_regs_t*)0)->_f3));   break;
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    case REG_F4:   return (sizeof (((ex_regs_t*)0)->_f4));   break;
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    case REG_F5:   return (sizeof (((ex_regs_t*)0)->_f5));   break;
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    case REG_F6:   return (sizeof (((ex_regs_t*)0)->_f6));   break;
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    case REG_F7:   return (sizeof (((ex_regs_t*)0)->_f7));   break;
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    case REG_FPS:  return (sizeof (((ex_regs_t*)0)->_fps));  break;
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#endif
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    case REG_CPSR: return (sizeof (((ex_regs_t*)0)->_cpsr)); break;
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    case REG_SPSVC: return (sizeof (((ex_regs_t*)0)->_spsvc)); break;
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    }
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    return 0;
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}
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/*
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 *  Given an exception number and a pointer to saved registers,
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 *  return a GDB signal value.
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 */
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int
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bsp_get_signal(int exc_nr, void *saved_regs)
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{
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  int sig = TARGET_SIGNAL_TRAP;
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  ex_regs_t *regs = (ex_regs_t *)saved_regs;
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  switch (exc_nr) {
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  case BSP_CORE_EXC_UNDEFINED_INSTRUCTION:
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  {
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      union arm_insn inst;
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      if (bsp_memory_read((void *)regs->_pc, 0, ARM_INST_SIZE * 8, 1, &(inst.word)) != 0)
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      {
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          /*
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           * We were able to read this address. It must be a valid address.
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           */
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          if (inst.word == BREAKPOINT_INSN)
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              sig = TARGET_SIGNAL_TRAP;
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      }
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      else
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          sig = TARGET_SIGNAL_ILL;
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  }
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  break;
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  case BSP_CORE_EXC_SOFTWARE_INTERRUPT:        sig = TARGET_SIGNAL_TRAP;    break;
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  case BSP_CORE_EXC_PREFETCH_ABORT:            sig = TARGET_SIGNAL_BUS;     break;
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  case BSP_CORE_EXC_DATA_ABORT:                sig = TARGET_SIGNAL_BUS;     break;
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  case BSP_CORE_EXC_ADDRESS_ERROR_26_BIT:      sig = TARGET_SIGNAL_BUS;     break;
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  case BSP_CORE_EXC_IRQ:                       sig = TARGET_SIGNAL_INT;     break;
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  case BSP_CORE_EXC_FIQ:                       sig = TARGET_SIGNAL_INT;     break;
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  default:                                     sig = TARGET_SIGNAL_TRAP;    break;
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  }
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187 
  return sig;
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}
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190 
 
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/*
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 * Set the PC value in the saved registers.
193 
 */
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void
195 
bsp_set_pc(unsigned long pc, void *saved_regs)
196 
{
197 
  ((ex_regs_t *)saved_regs)->_pc = pc;
198 
}
199 
 
200 
 
201 
/*
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 * Get the PC value from the saved registers.
203 
 */
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unsigned long
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bsp_get_pc(void *saved_regs)
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{
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  return ((ex_regs_t *)saved_regs)->_pc;
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}

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