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//==========================================================================

//

//      if_i82559.c

//

//      Intel 82559 ethernet driver

//

//==========================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.

// Copyright (C) 2002, 2003 Gary Thomas

//

// eCos is free software; you can redistribute it and/or modify it under

// the terms of the GNU General Public License as published by the Free

// Software Foundation; either version 2 or (at your option) any later version.

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//

// You should have received a copy of the GNU General Public License along

// with eCos; if not, write to the Free Software Foundation, Inc.,

// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

//

// As a special exception, if other files instantiate templates or use macros

// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

// by itself cause the resulting work to be covered by the GNU General Public

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// this file might be covered by the GNU General Public License.

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// at http://sources.redhat.com/ecos/ecos-license/

// -------------------------------------------

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//####BSDCOPYRIGHTBEGIN####

//

// -------------------------------------------

//

// Portions of this software may have been derived from OpenBSD or

// other sources, and are covered by the appropriate copyright

// disclaimers included herein.

//

// -------------------------------------------

//

//####BSDCOPYRIGHTEND####

//==========================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):    hmt, gthomas

// Contributors: Ron Spence, Pacific Softworks, jskov

// Date:         2000-02-01

// Purpose:      

// Description:  hardware driver for 82559 Intel PRO/100+ ethernet

// Notes:        CU commands such as dump and config should, according

//               to the docs, set the CU active state while executing.

//               That does not seem to be the case though, and the

//               driver polls the completion bit in the packet status

//               word instead.

//

//               Platform code may provide this vector:

//               CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT if it

//               requires the interrupts to be handled via demuxers

//               attached to a distinct interrupt.

//

//               Platform code may alternatively define:

//               CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL if it is necessary

//               to demux all interrupt sources - for example if they are

//               wire-or'd together on some hardware but distinct on

//               others.  In this circumstance it is permitted for

//               cyg_pci_translate_interrupt [HAL_PCI_TRANSLATE_INTERRUPT]

//               to return invalid for 2nd and subsequent devices.

//

//               Platform code can also define these three:

//               CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old)

//               CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old)

//               CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559)

//               which are particularly useful when nested interrupt

//               management is needed (which is always IMHO).

//

//               Platform code can define this:

//               CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559)

//               to detect a dropped interrupt and loop again or

//               direct-call the DSR to reschedule the delivery routine.

//               Only a problem on edge-triggered interrupt systems.

//

//               Platform code can also provide this macro:

//               CYGPRI_DEVS_ETH_INTEL_I82559_INTERRUPT_ACK_LOOP(p_i82559)

//               to handle delaying for acks to register on the interrupt

//               controller as necessary on the EBSA.

//

//               Platform can define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA()

//               as an external means to get ESAs, possibly from RedBoot

//               configuration info that's stored in flash memory.

//

//               Platform def CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM

//               removes all code for dealing with the EEPROM for those

//               targets where there is none fitted.  Either an external

//               means to get ESAs should be used, or we must rely on

//               hard-wiring the ESA's into each executable by means of the

//               usual CDL configuration.

//

//               Platform def CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM

//               is for hardware with multiple devices, but only one with a

//               serial EEPROM installed.  The 2nd device would get either

//               the same ESA - because they are certain to be on different

//               segment and internets - or the same ESA incremented by

//               CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST.

//               CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM should be the

//               number (0 or 1) of the device that does have the EEPROM.

//

//               CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS enables

//               checking code for breaks in the physical address of PCI

//               window memory.  This can happen on some boards where a

//               smaller SDRAM is fitted than the hardware allows, so some

//               higher-order address bits are ignored.  We make SDRAM

//               contiguous in mapped memory, but what the i82559 sees

//               might be discontiguous.  The checking code skips any

//               allocated chunk who appears to contain such a break, and

//               tries again.

//

//               CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT( int32 )

//               CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED( int32 ) if

//               both defined give the driver a means to detect that we

//               have been fixated on the same transmit operation for too

//               long - we missed an interrupt or the device crashed.  The

//               int32 argument is used to hold a eg. the value of a

//               fast-running hardware timer.

//

//               CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO if PCI IO

//               access is not affected by CPU endianess.

//

//        FIXME: replace -1/-2 return values with proper E-defines

//        FIXME: For 82557/8 compatibility i82559_configure() function

//               probably needs some tweaking - config bits differ

//               slightly but crucially.

//        FIXME: EEPROM code not tested on a BE system.

//

//####DESCRIPTIONEND####

//

//==========================================================================

#include <pkgconf/system.h>

#ifdef CYGPKG_IO_ETH_DRIVERS

#include <pkgconf/io_eth_drivers.h>

#endif

#include <pkgconf/devs_eth_intel_i82559.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/infra/cyg_ass.h>

#include <cyg/hal/hal_arch.h>

#include <cyg/hal/hal_intr.h>

#include <cyg/infra/diag.h>

#include <cyg/hal/hal_if.h>

#include <cyg/hal/drv_api.h>

#include <cyg/io/eth/netdev.h>

#include <cyg/io/eth/eth_drv.h>

#ifdef CYGPKG_NET

#include <pkgconf/net.h>

#include <net/if.h>  /* Needed for struct ifnet */

#endif

#ifdef CYGPKG_IO_PCI

#include <cyg/io/pci.h>

// So we can check the validity of the PCI window against the MLTs opinion,

// and thereby what the malloc heap consumes willy-nilly:

#include CYGHWR_MEMORY_LAYOUT_H

#else

#error "Need PCI package here"

#endif

// Exported statistics and the like

#include <cyg/devs/eth/i82559_info.h>

#include <cyg/io/eth/eth_drv_stats.h>

#include CYGDAT_DEVS_ETH_INTEL_I82559_INL

// ------------------------------------------------------------------------

// Check on the environment.

// 

// These are not CDL type config points; they are set up for your platform

// in the platform driver's include file and that's that.  These messages

// are for the eCos driver writer, not config tool users.

#ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL

#ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT

#error Both a separate demux interrupt *and* DEMUX_ALL are defined

#endif

#endif

#ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM

#ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM

#error This platform has no EEPROM, yet WRITE_EEPROM is enabled

#endif

#endif

#ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM

#ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM

#error This platform has no EEPROM, yet it also HAS_ONE_EEPROM

#endif

#endif

// ------------------------------------------------------------------------

#ifdef CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER

#define DEBUG          // Startup printing mainly

#define DEBUG_EE       // Some EEPROM specific retries &c

#if (CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER > 1)

#define DEBUG_82559 // This one prints stuff as packets come and go

#endif

#endif

#ifdef CYGDBG_USE_ASSERTS

static struct {

    int can_send;

    int deliver;

    int stats;

    int waitcmd_timeouts;

    int waitcmd_timeouts_cu;

    int lockup_timeouts;

    int bad_cu_idles;

} missed_interrupt = { 0,0,0, 0,0, 0, 0 };

#endif

#define os_printf diag_printf

#define db_printf diag_printf

// ------------------------------------------------------------------------

//

//                             MEMORY ADDRESSING

// 

// There is scope for confusion here; we deal with LE/BE systems and

// addressing issues in two separate ways depending on the type of access

// in question.

//

// 1) IO-style access to the device regsiters over the PCI bus

// 2) Memory access to build and read the structures in shared memory

// 

// In detail:

// 

// 1) IO-style access to the device regsiters over the PCI bus

// 

// All such access is via macros which perform byte-swapping as necessary

// for the endianness of the CPU.  These macros are called INL, INW, INB

// and OUTL, OUTW, OUTB - for Long (32) Word (16) and Byte (8).  Intel

// nomenclature seems to have crept in here for shorts.

// 

// Consequently, all the constants only have to be expressed once, in their

// true LE format - bit 15 is 0x8000, bit 0 is 1.

// 

// All the offsets are also only expressed once.  This is OK so long as GIB

// endian addressing (sic, see below) is not employed - or so long as is

// does not affect the PCI bus accesses.

//

// 

// 2) Memory access to build and read the structures in shared memory

// 

// These accesses are by means of peek and poke to an address created from

// a base + offset.  No swapping occurs within the access so all constants

// and flags need to be defined twice, once for BE and once for LE

// accesses.  Worse, for BE, constants need to be defined in flavours for

// 16-bit versus 32-bit accesses, ie. 0x8000 sets bit 7 only in BE; for a

// 32-bit access you must instead write 0x80000000 to set bit 7.

//

// Thus all constants are defined twice depending on the CPU's endianness.

//

// For most BE/LE machines, this is sufficient; the layout of memory is the

// same.  Specifically, within a 32-bit word, byte[0] will be data[0:7],

// short[0] will be data [0:15] and so on.  &byte[0] == &short[0] == &word

// regardless.  But data[0:7] *OF THE MEMORY SYSTEM* will hold either the

// LSbyte (0xFF) on a LE machine, and the MSbyte (0xFF000000) on a BE

// machine, for a 32-bit access.

// 

// It is in terms of the memory system that the i82559 defines its view of

// the world.

// 

// Therefore the structure layouts remain the same for both BE and LE

// machines.  This means that the offsets for, specifically, the status

// word in command blocks is always zero, and the offset for the command

// word is always two.

//

// But there is one furter variant: so-called GIB endian.  (BIG endian

// backwards) Some architectures support BE only for software

// compatibility; they allow code to run which relies on overlaid C

// structures behaving in a certain way; specifically

//     *(char *)&i == (i >> 24)

// ARM's BE mode is an example of this.

// 

// But while such an operation would use data[0:7] for the char access in a

// true BE or any LE system, in a GE system, data[24:31] are used here.

// The implementation is that for memory accesses, A0 and A1 are inverted

// before going outside to the memory system.  So if &i == 0x1000,

// accessing i uses address 0x1000, A0 and A1 being ignored for a 32-bit

// access.  But the 8-bit access to *(char *)&i also uses 0x1000 for the

// address as the code sees it, the memory system sees a byte request for

// address 0x1003, thus picking up the MSbyte, from data[24:31].

//

// For such addressing, offsets need to be redefined to swap bytes and

// shorts within words.  Therefore offsets are defined twice, once for

// "normal" addressing, and once for "GIB endian" addressing.

//

// FIXME: this BE/GE configuration probably won't work with an ARM in its

// BE mode - because that will define the global BE flags, yet it's not

// true BE, it's GE.

// Perhaps a solution whereby the GE flag CYG_ADDRESSING_IS_GIBENDIAN

// overrides the BYTEORDER choices would be good; we want the constants to

// be LE, but address offsets to be swapped per GE.

//

// Essay ends.

//

// ------------------------------------------------------------------------

// I/O access macros as inlines for type safety

#if (CYG_BYTEORDER == CYG_MSBFIRST)

#define HAL_CTOLE32(x)  ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))

#define HAL_LE32TOC(x)  ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))

#define HAL_CTOLE16(x)  ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))

#define HAL_LE16TOC(x)  ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))

#else

// Maintaining the same styleee as above...

#define HAL_CTOLE32(x)  ((((x))))

#define HAL_LE32TOC(x)  ((((x))))

#define HAL_CTOLE16(x)  ((((x))))

#define HAL_LE16TOC(x)  ((((x))))

#endif

#if (CYG_BYTEORDER == CYG_MSBFIRST) && !defined(CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO)

static inline void OUTB(cyg_uint8 value, cyg_uint32 io_address)

{

    HAL_WRITE_UINT8( io_address, value);

}

static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)

{

    HAL_WRITE_UINT16( io_address, (((value & 0xff) << 8) | ((value & 0xff00) >> 8)) );

}

static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)

{

    HAL_WRITE_UINT32( io_address,

                      ((((value) & 0xff) << 24) | (((value) & 0xff00) << 8) | (((value) & 0xff0000) >> 8) | (((value) >> 24) & 0xff)) );

}

static inline cyg_uint8 INB(cyg_uint32 io_address)

{

    cyg_uint8 d;

    HAL_READ_UINT8( io_address, d );

    return d;

}

static inline cyg_uint16 INW(cyg_uint32 io_address)

{

    cyg_uint16 d;

    HAL_READ_UINT16( io_address, d );

    return (((d & 0xff) << 8) | ((d & 0xff00) >> 8));

}

static inline cyg_uint32 INL(cyg_uint32 io_address)

{

    cyg_uint32 d;

    HAL_READ_UINT32( io_address, d );

    return ((((d) & 0xff) << 24) | (((d) & 0xff00) << 8) | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff));

}

#else

static inline void OUTB(cyg_uint8  value, cyg_uint32 io_address)

{   HAL_WRITE_UINT8( io_address, value );   }

static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)

{   HAL_WRITE_UINT16( io_address, value );   }

static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)

{   HAL_WRITE_UINT32( io_address, value );   }

static inline cyg_uint8  INB(cyg_uint32 io_address)

 {   cyg_uint8  _t_; HAL_READ_UINT8(  io_address, _t_ ); return _t_;   }

static inline cyg_uint16 INW(cyg_uint32 io_address)

 {   cyg_uint16 _t_; HAL_READ_UINT16( io_address, _t_ ); return _t_;   }

static inline cyg_uint32 INL(cyg_uint32 io_address)

 {   cyg_uint32 _t_; HAL_READ_UINT32( io_address, _t_ ); return _t_;   }

#endif // byteorder

// ------------------------------------------------------------------------

// Macros for writing shared memory structures - no need for byte flipping

#define READMEM8(   _reg_, _val_ ) ((_val_) = *((volatile CYG_BYTE *)(_reg_)))

#define WRITEMEM8(  _reg_, _val_ ) (*((volatile CYG_BYTE *)(_reg_)) = (_val_))

#define READMEM16(  _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD16 *)(_reg_)))

#define WRITEMEM16( _reg_, _val_ ) (*((volatile CYG_WORD16 *)(_reg_)) = (_val_))

#define READMEM32(  _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD32 *)(_reg_)))

#define WRITEMEM32( _reg_, _val_ ) (*((volatile CYG_WORD32 *)(_reg_)) = (_val_))

// ------------------------------------------------------------------------

// Map from CPU-view addresses to PCI-bus master's view - however that is:

#ifdef CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS

#define VIRT_TO_BUS( _x_ ) CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ )

#else // use default mappings: get a physical address to give to the device

#define VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)(_x_))

static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)

{ return CYGARC_PHYSICAL_ADDRESS(p_memory);    }

#endif // not defined CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS

// ------------------------------------------------------------------------

//                                                                      

//                   82559 REGISTER OFFSETS (I/O SPACE)                 

//                                                                      

// ------------------------------------------------------------------------

#define SCBStatus       0               // Rx/Command Unit Status *Word*

#define SCBIntAckByte   1               // Rx/Command Unit STAT/ACK byte

#define SCBCmd          2               // Rx/Command Unit Command *Word*

#define SCBIntrCtlByte  3               // Rx/Command Unit Intr.Control Byte

#define SCBPointer      4               // General purpose pointer.

#define SCBPort         8               // Misc. commands and operands.

#define SCBflash        12              // Flash memory control.

#define SCBeeprom       14              // EEPROM memory control.

#define SCBCtrlMDI      16              // MDI interface control.

#define SCBEarlyRx      20              // Early receive byte count.

#define SCBGenControl   28              // 82559 General Control Register

#define SCBGenStatus    29              // 82559 General Status register

// ------------------------------------------------------------------------

//

//               82559 SCB STATUS WORD DEFNITIONS

//

// ------------------------------------------------------------------------

#define SCB_STATUS_CX   0x8000          // CU finished command (transmit)

#define SCB_STATUS_FR   0x4000          // frame received

#define SCB_STATUS_CNA  0x2000          // CU left active state

#define SCB_STATUS_RNR  0x1000          // receiver left ready state

#define SCB_STATUS_MDI  0x0800          // MDI read/write cycle done

#define SCB_STATUS_SWI  0x0400          // software generated interrupt

#define SCB_STATUS_FCP  0x0100          // flow control pause interrupt

#define SCB_INTACK_MASK 0xFD00          // all the above

#define SCB_INTACK_MASK_BYTE 0xFD       // all the above

#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)

#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)

// ------------------------------------------------------------------------

//

//               SYSTEM CONTROL BLOCK COMMANDS

//

// ------------------------------------------------------------------------

// CU COMMANDS

#define CU_NOP          0x0000

#define CU_START        0x0010

#define CU_RESUME       0x0020

#define CU_STATSADDR    0x0040          // Load Dump Statistics ctrs addr

#define CU_SHOWSTATS    0x0050          // Dump statistics counters.

#define CU_ADDR_LOAD    0x0060          // Base address to add to CU commands

#define CU_DUMPSTATS    0x0070          // Dump then reset stats counters.

// RUC COMMANDS

#define RUC_NOP         0x0000

#define RUC_START       0x0001

#define RUC_RESUME      0x0002

#define RUC_ABORT       0x0004

#define RUC_ADDR_LOAD   0x0006          // (seems not to clear on acceptance)

#define RUC_RESUMENR    0x0007

#define CU_CMD_MASK     0x00f0

#define RU_CMD_MASK     0x0007

#define SCB_M           0x0100          // 0 = enable interrupt, 1 = disable

#define SCB_SWI         0x0200          // 1 - cause device to interrupt

#define SCB_BYTE_M        0x01          // 0 = enable interrupt, 1 = disable

#define SCB_BYTE_SWI      0x02          // 1 - cause device to interrupt

#define CU_STATUS_MASK  0x00C0

#define RU_STATUS_MASK  0x003C

#define RU_STATUS_IDLE  (0<<2)

#define RU_STATUS_SUS   (1<<2)

#define RU_STATUS_NORES (2<<2)

#define RU_STATUS_READY (4<<2)

#define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))

#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))

#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))

#define MAX_MEM_RESERVED_IOCTL 1000

// ------------------------------------------------------------------------

//

//               82559 PORT INTERFACE COMMANDS

//

// ------------------------------------------------------------------------

#define I82559_RESET            0x00000000 // software reset

#define I82559_SELFTEST         0x00000001 // 82559 selftest command

#define I82559_SELECTIVE_RESET  0x00000002

#define I82559_DUMP             0x00000003

#define I82559_DUMP_WAKEUP      0x00000007

// ------------------------------------------------------------------------

//

//                   82559 EEPROM INTERFACE

//

// ------------------------------------------------------------------------

//  EEPROM_Ctrl bits.

#define EE_SHIFT_CLK    0x01            // EEPROM shift clock.

#define EE_CS           0x02            // EEPROM chip select.

#define EE_DATA_WRITE   0x04            // EEPROM chip data in.

#define EE_DATA_READ    0x08            // EEPROM chip data out.

#define EE_ENB          (0x4800 | EE_CS)

// Delay between EEPROM clock transitions.

#define eeprom_delay(usec)              udelay(usec);

// The EEPROM commands include the always-set leading bit.

#define EE_WRITE_CMD(a)     (5 << (a))

#define EE_READ_CMD(a)      (6 << (a))

#define EE_ERASE_CMD(a)     (7 << (a))

#define EE_WRITE_EN_CMD(a)  (19 << ((a)-2))

#define EE_WRITE_DIS_CMD(a) (16 << ((a)-2))

#define EE_ERASE_ALL_CMD(a) (18 << ((a)-2))

#define EE_TOP_CMD_BIT(a)      ((a)+2) // Counts down to zero

#define EE_TOP_DATA_BIT        (15)    // Counts down to zero

#define EEPROM_ENABLE_DELAY (10) // Delay at chip select

#define EEPROM_SK_DELAY  (4) // Delay between clock edges *and* data

                             // read or transition; 3 of these per bit.

#define EEPROM_DONE_DELAY (100) // Delay when all done

// ------------------------------------------------------------------------

//

//               RECEIVE FRAME DESCRIPTORS

//

// ------------------------------------------------------------------------

// The status is split into two shorts to get atomic access to the EL bit;

// the upper word is not written by the device, so we can just hit it,

// leaving the lower word (which the device updates) alone.  Otherwise

// there's a race condition between software moving the end-of-list (EL)

// bit round and the device writing into the previous slot.

#if (CYG_BYTEORDER == CYG_MSBFIRST)

// Note that status bits are endian converted - so we don't need to

// fiddle the byteorder when accessing the status word!

#define RFD_STATUS_EL   0x00000080      // 1=last RFD in RFA

#define RFD_STATUS_S    0x00000040      // 1=suspend RU after receiving frame

#define RFD_STATUS_H    0x00001000      // 1=RFD is a header RFD

#define RFD_STATUS_SF   0x00000800      // 0=simplified, 1=flexible mode

#define RFD_STATUS_C    0x00800000      // completion of received frame

#define RFD_STATUS_OK   0x00200000      // frame received with no errors

#define RFD_STATUS_HI_EL   0x0080       // 1=last RFD in RFA

#define RFD_STATUS_HI_S    0x0040       // 1=suspend RU after receiving frame

#define RFD_STATUS_HI_H    0x1000       // 1=RFD is a header RFD

#define RFD_STATUS_HI_SF   0x0800       // 0=simplified, 1=flexible mode

#define RFD_STATUS_LO_C    0x0080       // completion of received frame

#define RFD_STATUS_LO_OK   0x0020       // frame received with no errors

#define RFD_COUNT_MASK     0x3fff

#define RFD_COUNT_F        0x4000

#define RFD_COUNT_EOF      0x8000

#define RFD_RX_CRC          0x00080000  // crc error

#define RFD_RX_ALIGNMENT    0x00040000  // alignment error

#define RFD_RX_RESOURCE     0x00020000  // out of space, no resources

#define RFD_RX_DMA_OVER     0x00010000  // DMA overrun

#define RFD_RX_SHORT        0x80000000  // short frame error

#define RFD_RX_LENGTH       0x20000000  //

#define RFD_RX_ERROR        0x10000000  // receive error

#define RFD_RX_NO_ADR_MATCH 0x04000000  // no address match

#define RFD_RX_IA_MATCH     0x02000000  // individual address does not match

#define RFD_RX_TCO          0x01000000  // TCO indication

#else // Little-endian

#define RFD_STATUS_EL   0x80000000      // 1=last RFD in RFA

#define RFD_STATUS_S    0x40000000      // 1=suspend RU after receiving frame

#define RFD_STATUS_H    0x00100000      // 1=RFD is a header RFD

#define RFD_STATUS_SF   0x00080000      // 0=simplified, 1=flexible mode

#define RFD_STATUS_C    0x00008000      // completion of received frame

#define RFD_STATUS_OK   0x00002000      // frame received with no errors

#define RFD_STATUS_HI_EL   0x8000       // 1=last RFD in RFA

#define RFD_STATUS_HI_S    0x4000       // 1=suspend RU after receiving frame

#define RFD_STATUS_HI_H    0x0010       // 1=RFD is a header RFD

#define RFD_STATUS_HI_SF   0x0008       // 0=simplified, 1=flexible mode

#define RFD_STATUS_LO_C    0x8000       // completion of received frame

#define RFD_STATUS_LO_OK   0x2000       // frame received with no errors

#define RFD_COUNT_MASK     0x3fff

#define RFD_COUNT_F        0x4000

#define RFD_COUNT_EOF      0x8000

#define RFD_RX_CRC          0x00000800  // crc error

#define RFD_RX_ALIGNMENT    0x00000400  // alignment error

#define RFD_RX_RESOURCE     0x00000200  // out of space, no resources

#define RFD_RX_DMA_OVER     0x00000100  // DMA overrun

#define RFD_RX_SHORT        0x00000080  // short frame error

#define RFD_RX_LENGTH       0x00000020  //

#define RFD_RX_ERROR        0x00000010  // receive error

#define RFD_RX_NO_ADR_MATCH 0x00000004  // no address match

#define RFD_RX_IA_MATCH     0x00000002  // individual address does not match

#define RFD_RX_TCO          0x00000001  // TCO indication

#endif // CYG_BYTEORDER

#ifndef CYG_ADDRESSING_IS_GIBENDIAN

// Normal addressing

#define RFD_STATUS       0

#define RFD_STATUS_LO    0

#define RFD_STATUS_HI    2

#define RFD_LINK         4

#define RFD_RDB_ADDR     8

#define RFD_COUNT       12

#define RFD_SIZE        14

#define RFD_BUFFER      16

#define RFD_SIZEOF      16

#else // CYG_ADDRESSING_IS_GIBENDIAN

// GIBENDIAN addressing; A0 and A1 are flipped:

#define RFD_STATUS       0

#define RFD_STATUS_LO    2              // swapped

#define RFD_STATUS_HI    0              // swapped

#define RFD_LINK         4

#define RFD_RDB_ADDR     8

#define RFD_COUNT       14              // swapped

#define RFD_SIZE        12              // swapped

#define RFD_BUFFER      16

#define RFD_SIZEOF      16

#endif // CYG_ADDRESSING_IS_GIBENDIAN

// ------------------------------------------------------------------------

//

//               TRANSMIT FRAME DESCRIPTORS

//

// ------------------------------------------------------------------------

#if (CYG_BYTEORDER == CYG_MSBFIRST)

// Note that CMD/STATUS bits are endian converted - so we don't need

// to fiddle the byteorder when accessing the CMD/STATUS word!

#define TxCB_CMD_TRANSMIT   0x0400      // transmit command

#define TxCB_CMD_SF         0x0800      // 0=simplified, 1=flexible mode

#define TxCB_CMD_NC         0x0010      // 0=CRC insert by controller

#define TxCB_CMD_I          0x0020      // generate interrupt on completion

#define TxCB_CMD_S          0x0040      // suspend on completion

#define TxCB_CMD_EL         0x0080      // last command block in CBL

#define TxCB_COUNT_MASK     0x3fff

#define TxCB_COUNT_EOF      0x8000

#else // Little-endian layout

#define TxCB_COUNT_MASK     0x3fff

#define TxCB_COUNT_EOF      0x8000

#define TxCB_CMD_TRANSMIT   0x0004      // transmit command

#define TxCB_CMD_SF         0x0008      // 0=simplified, 1=flexible mode

#define TxCB_CMD_NC         0x0010      // 0=CRC insert by controller

#define TxCB_CMD_I          0x2000      // generate interrupt on completion

#define TxCB_CMD_S          0x4000      // suspend on completion

#define TxCB_CMD_EL         0x8000      // last command block in CBL

#endif // CYG_BYTEORDER

#ifndef CYG_ADDRESSING_IS_GIBENDIAN

// Normal addressing

#define TxCB_STATUS          0

#define TxCB_CMD             2

#define TxCB_LINK            4

#define TxCB_TBD_ADDR        8

#define TxCB_COUNT          12

#define TxCB_TX_THRESHOLD   14

#define TxCB_TBD_NUMBER     15

#define TxCB_BUFFER         16

#define TxCB_SIZEOF         16

#else // CYG_ADDRESSING_IS_GIBENDIAN

// GIBENDIAN addressing; A0 and A1 are flipped:

#define TxCB_STATUS          2          // swapped

#define TxCB_CMD             0          // swapped

#define TxCB_LINK            4

#define TxCB_TBD_ADDR        8

#define TxCB_COUNT          14          // swapped

#define TxCB_TX_THRESHOLD   13          // swapped

#define TxCB_TBD_NUMBER     12          // swapped

#define TxCB_BUFFER         16

#define TxCB_SIZEOF         16

#endif // CYG_ADDRESSING_IS_GIBENDIAN

// ------------------------------------------------------------------------

//

//                   STRUCTURES ADDED FOR PROMISCUOUS MODE

//

// ------------------------------------------------------------------------

#if (CYG_BYTEORDER == CYG_MSBFIRST)

// Note CFG CMD and STATUS swapped, so no need for endian conversion

// in code.

#define CFG_CMD_EL         0x0080

#define CFG_CMD_SUSPEND    0x0040

#define CFG_CMD_INT        0x0020

#define CFG_CMD_IAS        0x0100       // individual address setup

#define CFG_CMD_CONFIGURE  0x0200       // configure

#define CFG_CMD_MULTICAST  0x0300       // Multicast-Setup

#define CFG_STATUS_C       0x0080

#define CFG_STATUS_OK      0x0020

#else // Little-endian 

#define CFG_CMD_EL         0x8000

#define CFG_CMD_SUSPEND    0x4000

#define CFG_CMD_INT        0x2000

#define CFG_CMD_IAS        0x0001       // individual address setup

#define CFG_CMD_CONFIGURE  0x0002       // configure

#define CFG_CMD_MULTICAST  0x0003       // Multicast-Setup

#define CFG_STATUS_C       0x8000

#define CFG_STATUS_OK      0x2000

#endif  // CYG_BYTEORDER

#ifndef CYG_ADDRESSING_IS_GIBENDIAN

// Normal addressing

#define CFG_STATUS          0

#define CFG_CMD             2

#define CFG_CB_LINK_OFFSET  4

#define CFG_BYTES           8

#define CFG_SIZEOF          32

#else // CYG_ADDRESSING_IS_GIBENDIAN

// GIBENDIAN addressing; A0 and A1 are flipped:

#define CFG_STATUS          2

#define CFG_CMD             0

#define CFG_CB_LINK_OFFSET  4

#define CFG_BYTES           8

#define CFG_SIZEOF          32

#endif // CYG_ADDRESSING_IS_GIBENDIAN

// Normal addressing

#define CFG_MC_LIST_BYTES 8

#define CFG_MC_LIST_DATA 10

// ------------------------------------------------------------------------

//

//                       STATISTICAL COUNTER STRUCTURE

//

// ------------------------------------------------------------------------

#ifdef KEEP_STATISTICS

STATISTICS statistics[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT];

I82559_COUNTERS i82559_counters[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT];

#endif // KEEP_STATISTICS

// ------------------------------------------------------------------------

//

//                      DEVICES AND PACKET QUEUES

//

// ------------------------------------------------------------------------

#define MAX_RX_PACKET_SIZE  1536        // maximum Rx packet size

#define MAX_TX_PACKET_SIZE  1536        // maximum Tx packet size

// ------------------------------------------------------------------------

// Use arrays provided by platform header to verify pointers.

#ifdef CYGDBG_USE_ASSERTS